Difference between revisions of "SPICARD Registers"
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(Created page with "== Registers == {| class="wikitable" border="1" ! NAME ! PHYSICAL ADDRESS ! WIDTH |- | REG_SPICARDFIFO | 0x1000D80C | 4 |}") |
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− | + | = Registers = | |
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
− | ! | + | ! Old3DS |
− | ! | + | ! Name |
− | ! | + | ! Address |
+ | ! Width | ||
+ | ! RW | ||
+ | ! Used by | ||
|- | |- | ||
− | | | + | | style="background: green" | Yes |
+ | | [[#NSPI_CNT|NSPI_CNT]] | ||
+ | | 0x1000D800 | ||
+ | | 4 | ||
+ | | RW | ||
+ | | | ||
+ | |- | ||
+ | | style="background: green" | Yes | ||
+ | | [[#NSPI_DONE|NSPI_DONE]] | ||
+ | | 0x1000D804 | ||
+ | | 4 | ||
+ | | RW | ||
+ | | | ||
+ | |- | ||
+ | | style="background: green" | Yes | ||
+ | | [[#NSPI_BLKLEN|NSPI_BLKLEN]] | ||
+ | | 0x1000D808 | ||
+ | | 4 | ||
+ | | RW | ||
+ | | | ||
+ | |- | ||
+ | | style="background: green" | Yes | ||
+ | | [[#NSPI_FIFO|NSPI_FIFO]] | ||
| 0x1000D80C | | 0x1000D80C | ||
| 4 | | 4 | ||
+ | | RW | ||
+ | | | ||
+ | |- | ||
+ | | style="background: green" | Yes | ||
+ | | [[#NSPI_STATUS|NSPI_STATUS]] | ||
+ | | 0x1000D810 | ||
+ | | 4 | ||
+ | | R | ||
+ | | | ||
+ | |- | ||
+ | | style="background: green" | Yes | ||
+ | | [[#NSPI_AUTOPOLL|NSPI_AUTOPOLL]] | ||
+ | | 0x1000D814 | ||
+ | | 4 | ||
+ | | RW | ||
+ | | | ||
+ | |- | ||
+ | | style="background: green" | Yes | ||
+ | | [[#NSPI_INT_MASK|NSPI_INT_MASK]] | ||
+ | | 0x1000D818 | ||
+ | | 4 | ||
+ | | W? | ||
+ | | | ||
+ | |- | ||
+ | | style="background: green" | Yes | ||
+ | | [[#NSPI_INT_STAT|NSPI_INT_STAT]] | ||
+ | | 0x1000D81C | ||
+ | | 4 | ||
+ | | RW | ||
+ | | | ||
+ | |} | ||
+ | |||
+ | == NSPI_CNT == | ||
+ | {| class="wikitable" border="1" | ||
+ | ! BIT | ||
+ | ! DESCRIPTION | ||
+ | |- | ||
+ | | 0-2 | ||
+ | | [[Filesystem_services#CardSpiBaudRate|Baud Rate]] | ||
+ | |- | ||
+ | | 6-7 | ||
+ | | Unused device select. | ||
+ | |- | ||
+ | | 12 | ||
+ | | [[Filesystem_services#CardSpiBusMode|Bus Mode]] | ||
+ | |- | ||
+ | | 13 | ||
+ | | Transfer Mode (0 = read, 1 = write) | ||
+ | |- | ||
+ | | 15 | ||
+ | | Trigger (0 = idle, 1 = busy) | ||
+ | |} | ||
+ | |||
+ | This register seems to have a bug where the lower 8 bits are shifted up by 16 when reading this register. | ||
+ | |||
+ | == NSPI_DONE == | ||
+ | Contains 1 when the SPI slave is selected. A 0 is written here on transfer end to deselect the slave. | ||
+ | |||
+ | == NSPI_BLKLEN == | ||
+ | {| class="wikitable" border="1" | ||
+ | ! BIT | ||
+ | ! DESCRIPTION | ||
+ | |- | ||
+ | | 0-20 | ||
+ | | Transfer size | ||
+ | |- | ||
+ | | 21-31 | ||
+ | | Unused | ||
+ | |} | ||
+ | |||
+ | == NSPI_FIFO == | ||
+ | {| class="wikitable" border="1" | ||
+ | ! BIT | ||
+ | ! DESCRIPTION | ||
+ | |- | ||
+ | | 0-31 | ||
+ | | Data | ||
+ | |} | ||
+ | |||
+ | This FIFO is one way (half-duplex). | ||
+ | |||
+ | == NSPI_STATUS == | ||
+ | {| class="wikitable" border="1" | ||
+ | ! BIT | ||
+ | ! DESCRIPTION | ||
+ | |- | ||
+ | | 0 | ||
+ | | FIFO Full (0 = not full, 1 = full) | ||
+ | |} | ||
+ | |||
+ | == NSPI_AUTOPOLL == | ||
+ | {| class="wikitable" border="1" | ||
+ | ! BIT | ||
+ | ! DESCRIPTION | ||
+ | |- | ||
+ | | 0-7 | ||
+ | | Command | ||
+ | |- | ||
+ | | 16-19 | ||
+ | | Timeout (Tries = 31<<Baudrate (from NSPI_CNT) + Timeout) | ||
+ | |- | ||
+ | | 24-26 | ||
+ | | Bit offset (0-7) | ||
+ | |- | ||
+ | | 30 | ||
+ | | Poll for a set or unset bit | ||
+ | |- | ||
+ | | 31 | ||
+ | | 1 = Enable/Busy | ||
+ | |} | ||
+ | |||
+ | This automatically sends a command to the device and compares the specified bit in the response with bit 30 until it matches or a timeout occurs. Nintendo uses a timeout of 10 which roughly equals 1 second. This is used in Process9 to poll the gamecard SPI flash status register for write operation finished or write enable. | ||
+ | |||
+ | == NSPI_INT_MASK == | ||
+ | {| class="wikitable" border="1" | ||
+ | ! BIT | ||
+ | ! DESCRIPTION | ||
+ | |- | ||
+ | | 0 | ||
+ | | Transfer finished (1 = disabled) | ||
+ | |- | ||
+ | | 1 | ||
+ | | Autopoll success (1 = disabled) | ||
+ | |- | ||
+ | | 2 | ||
+ | | Autopoll timeout (1 = disabled) | ||
+ | |} | ||
+ | |||
+ | == NSPI_INT_STAT == | ||
+ | {| class="wikitable" border="1" | ||
+ | ! BIT | ||
+ | ! DESCRIPTION | ||
+ | |- | ||
+ | | 0 | ||
+ | | Transfer finished (also fires on each autopoll try?) | ||
+ | |- | ||
+ | | 1 | ||
+ | | Autopoll success | ||
+ | |- | ||
+ | | 2 | ||
+ | | Autopoll timeout | ||
|} | |} | ||
+ | |||
+ | [[IRQ_Registers|Interrupt]] ID 23 is fired when any of the bits change to 1 except for interrupts masked in [[#NSPI_INT_MASK|NSPI_INT_MASK]]. Writing 1 to a bit in this register aknowledges the interrupt. |
Latest revision as of 00:08, 15 February 2021
Registers[edit]
Old3DS | Name | Address | Width | RW | Used by |
---|---|---|---|---|---|
Yes | NSPI_CNT | 0x1000D800 | 4 | RW | |
Yes | NSPI_DONE | 0x1000D804 | 4 | RW | |
Yes | NSPI_BLKLEN | 0x1000D808 | 4 | RW | |
Yes | NSPI_FIFO | 0x1000D80C | 4 | RW | |
Yes | NSPI_STATUS | 0x1000D810 | 4 | R | |
Yes | NSPI_AUTOPOLL | 0x1000D814 | 4 | RW | |
Yes | NSPI_INT_MASK | 0x1000D818 | 4 | W? | |
Yes | NSPI_INT_STAT | 0x1000D81C | 4 | RW |
NSPI_CNT[edit]
BIT | DESCRIPTION |
---|---|
0-2 | Baud Rate |
6-7 | Unused device select. |
12 | Bus Mode |
13 | Transfer Mode (0 = read, 1 = write) |
15 | Trigger (0 = idle, 1 = busy) |
This register seems to have a bug where the lower 8 bits are shifted up by 16 when reading this register.
NSPI_DONE[edit]
Contains 1 when the SPI slave is selected. A 0 is written here on transfer end to deselect the slave.
NSPI_BLKLEN[edit]
BIT | DESCRIPTION |
---|---|
0-20 | Transfer size |
21-31 | Unused |
NSPI_FIFO[edit]
BIT | DESCRIPTION |
---|---|
0-31 | Data |
This FIFO is one way (half-duplex).
NSPI_STATUS[edit]
BIT | DESCRIPTION |
---|---|
0 | FIFO Full (0 = not full, 1 = full) |
NSPI_AUTOPOLL[edit]
BIT | DESCRIPTION |
---|---|
0-7 | Command |
16-19 | Timeout (Tries = 31<<Baudrate (from NSPI_CNT) + Timeout) |
24-26 | Bit offset (0-7) |
30 | Poll for a set or unset bit |
31 | 1 = Enable/Busy |
This automatically sends a command to the device and compares the specified bit in the response with bit 30 until it matches or a timeout occurs. Nintendo uses a timeout of 10 which roughly equals 1 second. This is used in Process9 to poll the gamecard SPI flash status register for write operation finished or write enable.
NSPI_INT_MASK[edit]
BIT | DESCRIPTION |
---|---|
0 | Transfer finished (1 = disabled) |
1 | Autopoll success (1 = disabled) |
2 | Autopoll timeout (1 = disabled) |
NSPI_INT_STAT[edit]
BIT | DESCRIPTION |
---|---|
0 | Transfer finished (also fires on each autopoll try?) |
1 | Autopoll success |
2 | Autopoll timeout |
Interrupt ID 23 is fired when any of the bits change to 1 except for interrupts masked in NSPI_INT_MASK. Writing 1 to a bit in this register aknowledges the interrupt.