3dbrew - User contributions [en]

GPU/Internal Registers

2017-03-15T16:23:46Z

Mtheall:

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-30
| Number of extra parameters (may be zero)
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| signed, X
|-
| 16-25
| signed, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = perspective, 1 = not perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U²
|-
| 2
| V
|-
| 3
| V²
|-
| 4
| (U + V) / 2
|-
| 5
| (U² + V²) / 2
|-
| 6
| sqrt(U² + V²)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-10
| 0x60
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset
|-
| 8-31
| 0xE0C080
|}

This register is used to set the procedural texture unit's offset.

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| fixed1.0.7, Red difference between current and next color table elements
|-
| 8-15
| fixed1.0.7, Green difference between current and next color table elements
|-
| 16-23
| fixed1.0.7, Blue difference between current and next color table elements
|-
| 24-31
| fixed1.0.7, Alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

Equation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|}

This register configures gas light shading in the line-of-sight direction.

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|}

This register is used to configure the gas depth direction attenuation proportion.

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20-22
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = false, 1 = true)
|-
| 1
| unsigned, Boolean register b1 value (0 = false, 1 = true)
|-
| 2
| unsigned, Boolean register b2 value (0 = false, 1 = true)
|-
| 3
| unsigned, Boolean register b3 value (0 = false, 1 = true)
|-
| 4
| unsigned, Boolean register b4 value (0 = false, 1 = true)
|-
| 5
| unsigned, Boolean register b5 value (0 = false, 1 = true)
|-
| 6
| unsigned, Boolean register b6 value (0 = false, 1 = true)
|-
| 7
| unsigned, Boolean register b7 value (0 = false, 1 = true)
|-
| 8
| unsigned, Boolean register b8 value (0 = false, 1 = true)
|-
| 9
| unsigned, Boolean register b9 value (0 = false, 1 = true)
|-
| 10
| unsigned, Boolean register b10 value (0 = false, 1 = true)
|-
| 11
| unsigned, Boolean register b11 value (0 = false, 1 = true)
|-
| 12
| unsigned, Boolean register b12 value (0 = false, 1 = true)
|-
| 13
| unsigned, Boolean register b13 value (0 = false, 1 = true)
|-
| 14
| unsigned, Boolean register b14 value (0 = false, 1 = true)
|-
| 15
| unsigned, Boolean register b15 value (0 = false, 1 = true)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

GPU/Internal Registers

2017-03-15T16:15:18Z

Mtheall:

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-30
| Number of extra parameters (may be zero)
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| signed, X
|-
| 16-25
| signed, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = perspective, 1 = not perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U²
|-
| 2
| V
|-
| 3
| V²
|-
| 4
| U + V
|-
| 5
| U² + V²
|-
| 6
| sqrt(U²*U² + V²*V²)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-10
| 0x60
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset
|-
| 8-31
| 0xE0C080
|}

This register is used to set the procedural texture unit's offset.

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| fixed1.0.7, Red difference between current and next color table elements
|-
| 8-15
| fixed1.0.7, Green difference between current and next color table elements
|-
| 16-23
| fixed1.0.7, Blue difference between current and next color table elements
|-
| 24-31
| fixed1.0.7, Alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

Equation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|}

This register configures gas light shading in the line-of-sight direction.

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|}

This register is used to configure the gas depth direction attenuation proportion.

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20-22
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = false, 1 = true)
|-
| 1
| unsigned, Boolean register b1 value (0 = false, 1 = true)
|-
| 2
| unsigned, Boolean register b2 value (0 = false, 1 = true)
|-
| 3
| unsigned, Boolean register b3 value (0 = false, 1 = true)
|-
| 4
| unsigned, Boolean register b4 value (0 = false, 1 = true)
|-
| 5
| unsigned, Boolean register b5 value (0 = false, 1 = true)
|-
| 6
| unsigned, Boolean register b6 value (0 = false, 1 = true)
|-
| 7
| unsigned, Boolean register b7 value (0 = false, 1 = true)
|-
| 8
| unsigned, Boolean register b8 value (0 = false, 1 = true)
|-
| 9
| unsigned, Boolean register b9 value (0 = false, 1 = true)
|-
| 10
| unsigned, Boolean register b10 value (0 = false, 1 = true)
|-
| 11
| unsigned, Boolean register b11 value (0 = false, 1 = true)
|-
| 12
| unsigned, Boolean register b12 value (0 = false, 1 = true)
|-
| 13
| unsigned, Boolean register b13 value (0 = false, 1 = true)
|-
| 14
| unsigned, Boolean register b14 value (0 = false, 1 = true)
|-
| 15
| unsigned, Boolean register b15 value (0 = false, 1 = true)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

NWMUDS:GetConnectionStatus

2016-04-07T18:45:49Z

Mtheall:

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x000B0000]
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code
|-
| 1
| Result code
|-
| 2-13
| Output 0x30-byte structure.
|}

=Output structure=
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| 0x0
| 0x4
| u32 status
|-
| 0x4
| 0x4
| ?
|-
| 0x8
| 0x2
| u16 NetworkNodeID for this device.
|-
| 0xA
| 0x22
| ?
|-
| 0x2C
| 0x1
| u8 total_nodes.
|-
| 0x2D
| 0x1
| u8 max_nodes, originally from the NetworkStruct.
|-
| 0x2E
| 0x2
| u16 node_bitmask. This is a bitmask of NetworkNodeIDs: bit0 for NetworkNodeID 0x1(host), bit1 for NetworkNodeID 0x2(first original client), and so on.
|}

==Status values==
{| class="wikitable" border="1"
|-
! Type
! Description
|-
| 0x3
| Not connected to any network as a host/client.
|-
| 0x6
| Connected to a network as a host.
|-
| 0x9
| Connected to a network as a client.
|-
| 0xA
| Connected to a network as a spectator.
|}

=Description=
This is mainly used when the event handle from [[NWMUDS:Initialize]] is signalled. This is also used before using [[NWMUDS:Bind]]. For certain user-processes this may be used during NWMUDS initialization as well.

NWMUDS:GetConnectionStatus

2016-04-07T18:35:57Z

Mtheall:

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x000B0000]
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code
|-
| 1
| Result code
|-
| 2-13
| Output 0x30-byte structure.
|}

=Output structure=
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| 0x0
| 0x4
| u32 status
|-
| 0x4
| 0x4
| ?
|-
| 0x8
| 0x2
| u16 NetworkNodeID for this device.
|-
| 0xA
| 0x22
| ?
|-
| 0x2C
| 0x1
| u8 total_nodes.
|-
| 0x2D
| 0x1
| u8 max_nodes, originally from the NetworkStruct.
|-
| 0x2E
| 0x2
| u16 node_bitmask. This is a bitmask of NetworkNodeIDs: bit0 for NetworkNodeID 0x1(host), bit1 for NetworkNodeID 0x2(first original client), and so on.
|}

==Status values==
{| class="wikitable" border="1"
|-
! Type
! Description
|-
| 0x3
| Not connected to any network as a host/client.
|-
| 0x6
| Connected to a network as a host.
|-
| 0x9
| Connected to a network as a client.
|}

=Description=
This is mainly used when the event handle from [[NWMUDS:Initialize]] is signalled. This is also used before using [[NWMUDS:Bind]]. For certain user-processes this may be used during NWMUDS initialization as well.

Firmware Archiving Project

2016-03-28T20:42:17Z

Mtheall: Add some older versions

Firmware Archiving Project

2016-03-28T19:56:02Z

Mtheall: got these

At some point under 2015, all old system titles were removed from the Nintendo update server NUS.

For archiving purposes, let's see how many we can recover from our harddrives. If you'd like to contribute please fill in the table below.

{| class="wikitable" border="1"
! Title.Version
! Owners
|-

|-
| 0004013000001502.3072
|mtheall
|-
| 0004013000001502.4098
|mtheall
|-
| 0004013000001502.5120
|mtheall
|-
| 0004013000001502.6148
|
|-
| 0004013000001502.8192
|
|-
| 0004013000001502.9217
|
|-
| 0004013000001503.0
|mtheall
|-
| 0004013000001602.3074
|mtheall
|-
| 0004013000001602.4098
|mtheall
|-
| 0004013000001602.5120
|mtheall
|-
| 0004013000001602.6146
|
|-
| 0004013000001602.7172
|
|-
| 0004013000001602.9216
|
|-
| 0004013000001602.10242
|
|-
| 0004013000001602.11265
|
|-
| 0004013000001702.4096
|mtheall
|-
| 0004013000001702.5122
|mtheall
|-
| 0004013000001702.6145
|mtheall
|-
| 0004013000001702.7168
|mtheall
|-
| 0004013000001702.8196
|
|-
| 0004013000001702.9220
|
|-
| 0004013000001702.10243
|
|-
| 0004013000001702.12290
|
|-
| 0004013000001702.13315
|
|-
| 0004013000001702.14342
|
|-
| 0004013000001703.0
|mtheall
|-
| 0004013000001802.3072
|mtheall
|-
| 0004013000001802.4098
|mtheall
|-
| 0004013000001802.5120
|
|-
| 0004013000001802.6144
|
|-
| 0004013000001802.7168
|
|-
| 0004013000001803.0
|mtheall
|-
| 0004013000001A02.2048
|mtheall
|-
| 0004013000001A02.3074
|mtheall
|-
| 0004013000001A02.4096
|mtheall
|-
| 0004013000001A02.5120
|
|-
| 0004013000001A02.6145
|
|-
| 0004013000001A03.0
|mtheall
|-
| 0004013000001B02.0
|mtheall
|-
| 0004013000001B02.1025
|mtheall
|-
| 0004013000001B02.2048
|
|-
| 0004013000001B02.3073
|
|-
| 0004013000001B03.0
|mtheall
|-
| 0004013000001C02.5120
|mtheall
|-
| 0004013000001C02.6145
|mtheall
|-
| 0004013000001C02.7168
|mtheall
|-
| 0004013000001C02.8196
|
|-
| 0004013000001C02.10240
|
|-
| 0004013000001C02.11264
|
|-
| 0004013000001C02.12294
|
|-
| 0004013000001C03.0
|mtheall
|-
| 0004013000001D02.4096
|mtheall
|-
| 0004013000001D02.5121
|mtheall
|-
| 0004013000001D02.6148
|
|-
| 0004013000001D02.7168
|
|-
| 0004013000001D02.9216
|
|-
| 0004013000001D02.10240
|
|-
| 0004013000001D03.0
|mtheall
|-
| 0004013000001E02.1024
|mtheall
|-
| 0004013000001E02.2049
|mtheall
|-
| 0004013000001E02.3076
|
|-
| 0004013000001E02.5120
|
|-
| 0004013000001E03.0
|mtheall
|-
| 0004013000001F02.4102
|mtheall
|-
| 0004013000001F02.5122
|mtheall
|-
| 0004013000001F02.6145
|mtheall
|-
| 0004013000001F02.7168
|
|-
| 0004013000001F02.8192
|
|-
| 0004013000001F03.0
|mtheall
|-
| 0004013000002002.0
|mtheall
|-
| 0004013000002002.1025
|mtheall
|-
| 0004013000002002.2048
|
|-
| 0004013000002102.0
|mtheall
|-
| 0004013000002102.1025
|mtheall
|-
| 0004013000002102.2048
|
|-
| 0004013000002103.0
|mtheall
|-
| 0004013000002202.5120
|mtheall
|-
| 0004013000002202.6146
|mtheall
|-
| 0004013000002202.7168
|mtheall
|-
| 0004013000002202.8192
|
|-
| 0004013000002202.9219
|
|-
| 0004013000002202.11264
|
|-
| 0004013000002203.0
|mtheall
|-
| 0004013000002302.1025
|mtheall
|-
| 0004013000002302.2049
|mtheall
|-
| 0004013000002302.3072
|
|-
| 0004013000002303.0
|mtheall
|-
| 0004013000002402.4101
|mtheall
|-
| 0004013000002402.5122
|mtheall
|-
| 0004013000002402.6145
|
|-
| 0004013000002402.7172
|
|-
| 0004013000002402.8192
|
|-
| 0004013000002402.9216
|
|-
| 0004013000002403.0
|mtheall
|-
| 0004013000002602.4097
|mtheall
|-
| 0004013000002602.5122
|mtheall
|-
| 0004013000002602.6144
|mtheall
|-
| 0004013000002602.7170
|mtheall
|-
| 0004013000002602.8193
|
|-
| 0004013000002602.9216
|
|-
| 0004013000002602.10240
|
|-
| 0004013000002702.2048
|mtheall
|-
| 0004013000002702.3073
|mtheall
|-
| 0004013000002702.4096
|
|-
| 0004013000002702.5120
|
|-
| 0004013000002703.0
|mtheall
|-
| 0004013000002802.3078
|mtheall
|-
| 0004013000002802.4099
|mtheall
|-
| 0004013000002802.5123
|
|-
| 0004013000002802.6145
|
|-
| 0004013000002802.7174
|
|-
| 0004013000002802.8192
|
|-
| 0004013000002902.5122
|mtheall
|-
| 0004013000002902.6145
|mtheall
|-
| 0004013000002902.7171
|
|-
| 0004013000002902.8192
|
|-
| 0004013000002902.9220
|
|-
| 0004013000002902.10245
|
|-
| 0004013000002902.12288
|
|-
| 0004013000002902.13318
|
|-
| 0004013000002903.0
|mtheall
|-
| 0004013000002A02.0
|mtheall
|-
| 0004013000002A02.1025
|mtheall
|-
| 0004013000002A02.2048
|
|-
| 0004013000002A03.0
|mtheall
|-
| 0004013000002B02.3072
|mtheall
|-
| 0004013000002B02.4098
|mtheall
|-
| 0004013000002B02.5124
|
|-
| 0004013000002B02.7169
|
|-
| 0004013000002C02.3074
|mtheall
|-
| 0004013000002C02.4100
|mtheall
|-
| 0004013000002C02.5120
|mtheall
|-
| 0004013000002C02.6148
|
|-
| 0004013000002C02.7174
|
|-
| 0004013000002C02.8195
|
|-
| 0004013000002C02.10249
|
|-
| 0004013000002C02.11267
|
|-
| 0004013000002C02.12296
|
|-
| 0004013000002C02.13313
|
|-
| 0004013000002C03.0
|mtheall
|-
| 0004013000002D02.5120
|mtheall
|-
| 0004013000002D02.6148
|mtheall
|-
| 0004013000002D02.7169
|mtheall
|-
| 0004013000002D02.8196
|
|-
| 0004013000002D02.9216
|
|-
| 0004013000002D02.10240
|
|-
| 0004013000002D03.0
|mtheall
|-
| 0004013000002D03.5120
|mtheall
|-
| 0004013000002E02.4096
|mtheall
|-
| 0004013000002E02.5121
|mtheall
|-
| 0004013000002E02.6144
|
|-
| 0004013000002E02.7168
|
|-
| 0004013000002E02.8192
|
|-
| 0004013000002E03.0
|mtheall
|-
| 0004013000002F02.4096
|mtheall
|-
| 0004013000002F02.5122
|mtheall
|-
| 0004013000002F02.6144
|
|-
| 0004013000002F02.7168
|
|-
| 0004013000002F02.8198
|
|-
| 0004013000002F03.0
|mtheall
|-
| 0004013000003102.1025
|mtheall
|-
| 0004013000003102.2049
|mtheall
|-
| 0004013000003102.3072
|mtheall
|-
| 0004013000003102.4096
|
|-
| 0004013000003102.5120
|
|-
| 0004013000003103.0
|mtheall
|-
| 0004013000003202.4096
|mtheall
|-
| 0004013000003202.5122
|mtheall
|-
| 0004013000003202.6145
|
|-
| 0004013000003202.7172
|
|-
| 0004013000003202.8192
|
|-
| 0004013000003202.9216
|
|-
| 0004013000003202.10240
|
|-
| 0004013000003203.0
|mtheall
|-
| 0004013000003302.4096
|mtheall
|-
| 0004013000003302.5121
|mtheall
|-
| 0004013000003302.6148
|
|-
| 0004013000003302.8192
|
|-
| 0004013000003302.9216
|
|-
| 0004013000003302.10246
|
|-
| 0004013000003302.11265
|
|-
| 0004013000003302.12289
|
|-
| 0004013000003303.0
|mtheall
|-
| 0004013000003402.5122
|mtheall
|-
| 0004013000003402.6146
|mtheall
|-
| 0004013000003402.7169
|mtheall
|-
| 0004013000003402.8193
|mtheall
|-
| 0004013000003402.9222
|
|-
| 0004013000003402.10240
|
|-
| 0004013000003402.11266
|
|-
| 0004013000003402.12289
|
|-
| 0004013000003402.13314
|
|-
| 0004013000003502.3072
|mtheall
|-
| 0004013000003502.4097
|mtheall
|-
| 0004013000003502.5120
|
|-
| 0004013000003502.6147
|
|-
| 0004013000003502.7168
|
|-
| 0004013000003702.1024
|mtheall
|-
| 0004013000003702.2049
|mtheall
|-
| 0004013000003702.3074
|
|-
| 0004013000003702.4096
|
|-
| 0004013000003702.5120
|
|-
| 0004013000003702.6148
|
|-
| 0004013000003802.1029
|
|-
| 0004013000003802.2050
|
|-
| 0004013000003802.3077
|
|-
| 0004013000003802.4099
|
|-
| 0004013000003802.6144
|
|-
| 0004013000003802.7168
|
|-
| 0004013000003802.8198
|
|-
| 0004013000004002.2053
|
|-
| 0004013000004002.4106
|
|-
| 0004013000004002.5121
|
|-
| 0004013000004002.6145
|
|-
| 0004013000004002.7168
|
|-
| 0004013000004002.8192
|
|-
| 0004013000008002.5121
|mtheall
|-
| 0004013000008002.6148
|mtheall
|-
| 0004013000008002.7168
|mtheall
|-
| 0004013000008002.8193
|mtheall
|-
| 0004013000008002.9216
|mtheall
|-
| 0004013000008002.10248
|
|-
| 0004013000008002.11268
|
|-
| 0004013000008002.12291
|
|-
| 0004013000008002.14336
|
|-
| 0004013000008002.15360
|
|-
| 0004013000008002.16390
|
|-
| 0004013000008002.17408
|
|-
| 0004013000008002.18433
|
|-
| 0004013000008002.19458
|
|-
| 0004013000008003.0
|mtheall
|-
| 0004013800000002.6677
|mtheall
|-
| 0004013800000002.7712
|mtheall
|-
| 0004013800000002.8758
|mtheall
|-
| 0004013800000002.9792
|mtheall
|-
| 0004013800000002.10833
|mtheall
|-
| 0004013800000002.11872
|mtheall
|-
| 0004013800000002.12916
|
|-
| 0004013800000002.13956
|
|-
| 0004013800000002.15047
|
|-
| 0004013800000002.17120
|
|-
| 0004013800000002.18182
|
|-
| 0004013800000002.19216
|
|-
| 0004013800000002.20262
|
|-
| 0004013800000002.21288
|
|-
| 0004013800000002.22313
|
|-
| 0004013800000002.23341
|
|-
| 0004013800000003.5632
|mtheall
|-
| 0004013800000102.4625
|mtheall
|-
| 0004013800000102.5681
|mtheall
|-
| 0004013800000102.6704
|mtheall
|-
| 0004013800000102.7762
|mtheall
|-
| 0004013800000102.8817
|mtheall
|-
| 0004013800000202.2576
|mtheall
|}

Homebrew Applications

2016-01-16T00:21:29Z

Mtheall: /* Applications */

==Installing==
Applications are installed by copying the necessary files to the 3ds/ folder in the root of the SD-card. Most applications come with two files:
* (app name).3dsx: The executable.
* (app name).smdh: The icon/metadata.

The [[Homebrew Launcher]] will scan the sdcard for all .3dsx files, but will only display an icon for those who have one according to the format described above.

==List==

===Official Launcher===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
|-
| [https://github.com/smealum/3ds_hb_menu Homebrew Launcher]
| Run homebrew on your 3DS!
| [[User:smea|smea]]
| [https://smealum.github.io/ninjhax2/boot.3dsx Here]
| Yes
|-
| [https://github.com/smealum/3ds_hb_menu Homebrew Starter Pack]
| Everything to get you started.
| [[User:smea|smea]]
| [https://smealum.github.io/ninjhax2/starter.zip Here]
| Yes
|}

===Applications===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
! width="10%" | Last Updated
|-
| [https://github.com/yellows8/3ds_homemenu_extdatatool 3DS HomeMenu extdata Tool]
| Tool for accessing the SD extdata which Home Menu uses. This essentially allows writing custom themes to extdata which get loaded at Home Menu startup.
| [[User:yellows8|yellows8]]
| [https://github.com/yellows8/3ds_homemenu_extdatatool/releases]
| Yes
|
|-
| [https://github.com/markwinap/3DS_Nyan_Cat 3DS Nyan Cat]
| 3DS Nyan Cat using LIBSF2D.
| [[User:markwinap|markwinap]]
| [https://www.dropbox.com/s/e400my3xm0zw74r/nyan_cat.zip?dl=0 Here]
| Yes
|
|-
| [https://gbatemp.net/threads/videahs-various-stuff.397562/ 3dsfetch]
| Small 3DS version of a popular Linux ricing script called screenfetch
| [[User:VideahGams|VideahGams]]
| [https://github.com/VideahGams/3dsfetch Here]
| [https://github.com/VideahGams/3dsfetch Yes]
|
|-
| [https://github.com/S3r1alpari4h/Brainfudge3DS Brainfudge]
| Alpha brainfuck interpreter
| [[User:s3r1alpari4h|V0idst4r]]
| [https://github.com/s3r1alpari4h/Brainfudge3DS/releases/ Here]
| [https://github.com/S3r1alpari4h/Brainfudge3DS Yes]
|
|-
| [https://github.com/plutooo/ctrrpc ctrrpc]
| A small and easily extensible RPC server/client written in C/Python. Allows you to quickly poke service-commands and syscalls over wifi from a Python shell on your PC. Useful during reverse-engineering.
| [[User:plutooo|plutoo]]
| N/A
| Yes
|
|-
| [https://github.com/yellows8/ctr-streaming-server ctr-streaming-server]
| This is a server which runs on a 3DS, which receives audio/video for playback. This can also send [[HID_Shared_Memory|HID]] state to the client (see the README) when enabled. The included parse_hidstream tool can be used to parse that HID data to simulate keyboard/mouse input events, via Linux uinput.
| [[User:yellows8|yellows8]]
| N/A
| Yes
|
|-
| [https://github.com/Rinnegatamante/CHMM2 Custom Home Menu Manager 2]
| Theme manager for Nintendo 3DS
| [[User:Rinnegatamante|Rinnegatamante]]
| [http://rinnegatamante.it/CHMM2.rar Here]
| Yes
|
|-
| [https://github.com/DownloadMii/DownloadMii DownloadMii]
| This is a WIP homebrew online store.
| [[User:filfat|filfat]]
| [https://www.downloadmii.com/download/#release Latest]
| Yes
|
|-
| [https://github.com/linoma/fb43ds fb43ds]
| This is a simple Facebook's chat client
| [[User:linoma|linoma]]
| [https://github.com/linoma/fb43ds Here]
| Yes
|
|-
| [https://github.com/Steveice10/FBI FBI]
| Open source CIA (un)installer.
| [[User:Steveice10|Steveice10]]
| [https://github.com/Steveice10/FBI/releases/ Here]
| Yes
|
|-
| [https://github.com/iamevn/for-anyone-who-walks-a-lot for-anyone-who-walks-a-lot]
| Tool to get past the 10 coin per day limit on earning Play Coins by walking.
| [[User:iamevn|iamevn]]
| [https://github.com/iamevn/for-anyone-who-walks-a-lot/releases Here]
| Yes
|
|-
| [https://github.com/mtheall/ftbrony ftBRONY]
| An FTP server.
| [https://github.com/mtheall mtheall]
| [https://github.com/mtheall/ftbrony/releases Here]
| Yes
|
|-
| [https://github.com/iamevn/FTP-3DS FTP-3DS]
| Fork of ftBRONY with a Nintendo theme.
| [[User:iamevn|iamevn]]
| [https://github.com/iamevn/FTP-3DS/releases Here]
| Yes
|
|-
| [https://github.com/smealum/ftPONY ftPONY]
| A basic FTP server, useful for testing new homebrew versions without swapping the SD card.
| [[User:smea|smea]]
| [https://mega.co.nz/#!nchBkL7B!T3vXnX4q8Uwp6APYYTDSZi2bkm25la-Qyz6j4CjsllI Here]
| Yes
|
|-
| [https://github.com/zeta0134/3ds-homebrew-browser Homebrew Browser]
| Download homebrew from the internet!
| [[User:cromo|cromo]] [[User:zeta0134|zeta0134]]
| [https://github.com/zeta0134/3ds-homebrew-browser/releases/tag/v0.1 Here]
| Yes
|
|-
|[https://github.com/meladroit/svdt svdt]
|Save Data Explorer/Manager
|[[User:meladroit|meladroit]]
|[https://github.com/meladroit/svdt/releases Here]
|Yes
|
|}

===Game Engines===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
! width="10%" | Last Updated
|-
| [https://gbatemp.net/threads/release-l%C3%B6vepotion-l%C3%96ve-api-for-3ds-homebrew-beta.397559/ LövePotion]
| An unofficial work in progress implementation of the LÖVE API for 3DS Homebrew
| [[User:VideahGams|VideahGams]]
| [https://github.com/VideahGams/LovePotion/releases Here]
| [https://github.com/VideahGams/LovePotion Yes]
|
|}

===Games===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
! width="10%" | Last Updated
|-
| [http://gbatemp.net/threads/release-100-boxes-2ds.384714/ 100 Boxes 2DS]
| Simple puzzle game.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/100Boxes2DS/100_Boxes_2DS.rar Here]
| Yes
|
|-
| [https://github.com/MrJPGames/2048-3D 2048-3D]
| "2048 was a big hit not so long ago, and I still see many people at my school playing it. So I thought it would be pretty cool to be able to play 2048 on the go on the 3DS."
| [[User:MrJPGames|Jasper Peters]]
| [https://github.com/MrJPGames/2048-3D/blob/master/2048-3D.3dsx?raw=true Here]
| Yes
|
|-
| [https://github.com/smealum/3dscraft 3DSCraft]
| Minecraft clone.
| [https://twitter.com/smealum smea]
| [http://smealum.github.io/3dscraft/downloads/3dscraft_141120.zip Here]
| Yes
|
|-
| [https://gbatemp.net/threads/preview-ld-34-port-antibounce.406361 Antibounce]
| Move your player to bounce around and collect coins. Go between screens through the holes in the sides of the floor. 3D can also be enabled.
| TurtleP
| [https://github.com/TurtleP/Antibounce/releases Here]
| [https://github.com/TurtleP/Antibounce Yes]
|
|-
| [https://github.com/UnsureSherlock/checkers3ds/tree/master checkers3ds]
| A buggy ASCII checkers game
| [[User:UnsureSherlock|UnsureSherlock]]
| [http://www.filedropper.com/checkers3ds Here]
| Yes
|
|-
| [https://gbatemp.net/threads/release-drawattack-networked-drawing-game.402291/ DrawAttack]
| Online multiplayer drawing game like pictionary.
| [[User:Cruel|Cruel]]
| [https://github.com/Cruel/DrawAttack/releases/latest Here]
| [https://github.com/Cruel/DrawAttack Yes]
| 11/16/15
|-
| [http://gbatemp.net/threads/release-hamsters-2ds.383457/ Hamsters 2DS]
| A hamster breeding game in text mode.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/Hamsters2DS/Hamsters_2DS.rar Here]
| No
|
|-
| [https://github.com/BHSPitMonkey/Helii3DS Helii]
| Fly a helicopter through a 2D tunnel! Ported from the Wii.
| [[User:BHSPitMonkey|BHSPitMonkey]]
| [https://github.com/BHSPitMonkey/Helii3DS/releases/ Here]
| [https://github.com/BHSPitMonkey/Helii3DS Yes]
| 9/18/15
|-
| [http://gowengamedev.com/insectoid-defense/ Insectoid Defense]
| A Sci-Fi Tower Defense game. This is merely a port of the Android/iOS/Windows Phone version.
| [http://www.3dbrew.org/wiki/User:Sgowen sgowen]
| [https://github.com/GowenGameDevOpenSource/insectoid-defense/releases/download/v1.0-all/insectoid-defense-3DS.zip Here]
| [https://github.com/GowenGameDevOpenSource/insectoid-defense Yes]
|
|-
| [https://gbatemp.net/threads/videahs-various-stuff.397562/ NumberFucker3DS]
| Simple math game, originally used as a debug game for LövePotion
| [[User:VideahGams|VideahGams]]
| [https://github.com/VideahGams/NumberFucker3DS Here]
| [https://github.com/VideahGams/NumberFucker3DS Yes]
|
|-
| [https://gbatemp.net/threads/release-mastermind-3ds.394710/#post-5611660 Mastermind 3DS]
| Mastermind on 3DS
| [[User:MrJPGames|Jasper Peters]]
| [https://github.com/MrJPGames/Mastermind-3DS/blob/master/Mastermind.zip?raw=true Here]
| Yes
|
|-
| [http://gbatemp.net/threads/release-minesweeper-2ds.384185/ Minesweeper 2DS]
| Minesweeper clone.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/Minesweeper2DS/Minesweeper_2DS.rar Here]
| Yes
|
|-
| [http://gbatemp.net/threads/release-paddle-puffle-3ds.392215/ Paddle Puffle 3DS]
| A port of [http://puffles.gatuno.mx Paddle Puffle] for the 3DS.
| Peanut42
| [http://puffles.gatuno.mx/releases/paddlepuffle3ds.zip Here]
| [https://github.com/gatuno/PaddlePuffle3DS Yes]
|
|-
| [http://gbatemp.net/threads/release-pixel-shuffle-2ds.398540/ Pixel Shuffle 2DS]
| Puzzle game.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/PixelShuffle2DS/Pixel_Shuffle_2DS.rar Here]
| Yes
|
|-
| [http://gbatemp.net/threads/release-pixel-swap-2ds.395749/ Pixel Swap 2DS]
| Relaxing Puzzle game.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/PixelSwap2DS/Pixel_Swap_2DS.rar Here]
| Yes
|
|-
| [https://github.com/smealum/portal3DS Portal3DS]
| An adaptation of [https://en.wikipedia.org/wiki/Portal_(video_game) Portal] for the 3DS.
| [https://twitter.com/smealum smea]
| N/A
| [https://github.com/smealum/portal3DS Yes]
|
|-
| [https://gbatemp.net/threads/release-reversi-othello-for-3ds.395442/ Reversi]
| [https://en.wikipedia.org/wiki/Reversi Reversi] for the 3DS.
| [[User:MrJPGames|Jasper Peters]]
| [https://github.com/MrJPGames/Othello-3DS/releases Here]
| [https://github.com/MrJPGames/Othello-3DS Yes]
|
|-
| [https://gbatemp.net/threads/release-space-fruit.399088/ Space Fruit]
| Hackathon game by 4 friends ported to 3DS. Asteroids but with fruit (kinda)
| TurtleP
| [https://github.com/TurtleP/Space_Fruit/releases Here]
| [https://github.com/TurtleP/Space_Fruit/tree/3DS Yes]
|
|-
| [http://gowengamedev.com/tappy-plane/ Tappy Plane]
| A Flappy Bird clone, but with a colorful plane. This is merely a port of the Android/iOS/Windows Phone version.
| [http://www.3dbrew.org/wiki/User:Sgowen sgowen]
| [https://github.com/GowenGameDevOpenSource/tappy-plane/releases/download/v1.0-all/tappy-plane-3DS.zip Here]
| [https://github.com/GowenGameDevOpenSource/tappy-plane Yes]
|
|-
| [http://gbatemp.net/threads/release-tilemap-2ds.386733/ TileMap 2DS]
| Puzzle game.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/TileMap2DS/TileMap_2DS.rar Here]
| Yes
|
|-
| [http://gbatemp.net/threads/release-tiles-2ds.385796/ Tiles 2DS]
| Puzzle game, Lights Out Like.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/Tiles2DS/Tiles_2DS.rar Here]
| Yes
|
|-
| [http://gbatemp.net/threads/trucmuche-2ds-09.404859// Trucmuche 2DS 09]
| Hidden Objects.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/Trucmuche2DS09/Trucmuche_2DS_09.rar Here]
| Yes
|
|-
| [https://github.com/Steveice10/WorldOf3DSand World of 3DSand]
| World of Sand clone.
| [[User:Steveice10|Steveice10]]
| [https://github.com/Steveice10/WorldOf3DSand/releases/ Here]
| Yes
|
|-
| [https://github.com/smealum/yeti3DS Yeti3DS]
| A quick and dirty port of Derek Evans' Yeti3D software rendering engine.
| [https://twitter.com/smealum smea]
| N/A
| Yes
|
|-
| [https://github.com/masterfeizz/ctrQuake ctrQuake]
| Unofficial port of Quake for the 3DS, fully playable.
| [https://twitter.com/masterfeizz MasterFeizz]
| [https://github.com/masterfeizz/ctrQuake/releases/ Here]
| Yes
|
|-
| [https://github.com/masterfeizz/EDuke3D EDuke3D]
| Unofficial port of EDuke32 for the Nintendo 3DS
| [https://twitter.com/masterfeizz MasterFeizz]
| [https://github.com/masterfeizz/EDuke3D/releases/ Here]
| Yes
|
|}

===Emulators===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
! width="10%" | Last Updated
|-
| [https://github.com/st4rk/3DNES 3DNES]
| An NES emulator. (No longer being worked on)
| St4rk
| [http://filetrip.net/3ds-downloads/homebrew/dl-3dnes-1-2-f32931.html Here]
| Yes
| March 2015
|-
| [https://github.com/StapleButter/blargSnes blargSnes]
| A Super Nintendo emulator. A compatibility list can be found [http://wiki.gbatemp.net/wiki/BlargSnes_Compatibility_List here].
| StapleButter
| [http://kuribo64.net/get.php?id=fYRTHLeS0pR3DXFw Here]
| Yes
| May 2015
|-
| [https://github.com/xerpi/CHIP-3DS CHIP-3DS]
| A simple and slow CHIP-8 emulator.
| xerpi
| [https://www.mediafire.com/?y94yjhzf70fsfsi Here]
| Yes
| March 2015
|-
| [https://github.com/shinyquagsire23/gpsp CitrAGB]
| Yet another GBA emulator.
| shinyquagsire23
| [https://www.dropbox.com/s/sxb7x34u58g4zo2/3ds.3dsx?dl=0 Here]
| Yes
| September 2015
|-
| [https://github.com/Steveice10/GameYob/ GameYob]
| A Game Boy (Color) emulator. A compatibility list can be found [http://wiki.gbatemp.net/wiki/GameYob_3DS_Compatibility_List here].
| Drenn/Steveice10
| [https://github.com/Steveice10/GameYob/releases Here]
| Yes
| November 2015
|-
| [https://github.com/mrdanielps/r3Ddragon r3Ddragon]
| A virtual boy emulator.
| mrdanielps
| [https://github.com/mrdanielps/r3Ddragon/releases/download/v0.85-preview.1/r3Ddragon.cia Here]
| Yes
| October 2015
|-
| [https://github.com/libretro/RetroArch RetroArch]
| A multisystem emulator. (GB, GBA, SNES, Genesis, CPS1, CPS2, etc.)
| libretro
| [http://buildbot.libretro.com/nightly/nintendo/3ds/ Here]
| Yes
| December 2015
|-
| [https://github.com/mgba-emu/mgba mGBA]
| A GBA emulator that runs good without kernel hax.
| endrift
| [https://mgba.io/nightlies.html Here]
| Yes
| December 2015
|}

===Icon Packs===
Icon Packs are SMDH Packs for homebrew apps
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Last Updated
|-
|Simplok
|The first 3DS Icon pack.
|link6155
|[http://1drv.ms/1EJCq2e Download]
| 7 September 2015
|-
|1LP
|Cool Icon Pack!.
|[[User:100pcrack|100pcrack]]
|[http://github.com/100pcrack/1LP/releases Releases]
| 27 November 2015
|}

===Demos===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
! width="10%" | Last Updated
|-
| cubedemo
| A short demo of Homebrew on 3ds with working sound.
| [[User:plutoo|plutoo]]
| [https://mega.co.nz/#!KUQFiQYA!pv8HDEyrmuX6Eyw2hW0opL7gf9Ztmjd9J5pPsvs_rD4 Here]
| No
|
|-
| Spine 2D
| Demo of [http://esotericsoftware.com/ Spine] 2D skeletal animations
| [[User:Cruel|Cruel]]
| [https://mega.nz/#!Xg411B5R!kcVHP69Ilggmjh4q5OYmr2cFvf5UGdHWA98-_VttDTo 3DSX] [https://mega.nz/#!z8gxHSQb!H0as1A4wqYrdKBhXJwdYik7nPd_msXJhz5N1CeZm1Iw CIA]
| No
|
|}
===Alternate Launchers===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
|-
| Mashers HBL
| Homebrew Launcher with a grid and folders support.
| [[User:Mashers|Mashers]]
| [http://gbatemp.net/threads/release-homebrew-launcher-with-grid-layout.397527/ Here]
| No
|}

Homebrew Applications

2016-01-16T00:19:57Z

Mtheall:

==Installing==
Applications are installed by copying the necessary files to the 3ds/ folder in the root of the SD-card. Most applications come with two files:
* (app name).3dsx: The executable.
* (app name).smdh: The icon/metadata.

The [[Homebrew Launcher]] will scan the sdcard for all .3dsx files, but will only display an icon for those who have one according to the format described above.

==List==

===Official Launcher===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
|-
| [https://github.com/smealum/3ds_hb_menu Homebrew Launcher]
| Run homebrew on your 3DS!
| [[User:smea|smea]]
| [https://smealum.github.io/ninjhax2/boot.3dsx Here]
| Yes
|-
| [https://github.com/smealum/3ds_hb_menu Homebrew Starter Pack]
| Everything to get you started.
| [[User:smea|smea]]
| [https://smealum.github.io/ninjhax2/starter.zip Here]
| Yes
|}

===Applications===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
! width="10%" | Last Updated
|-
| [https://github.com/yellows8/3ds_homemenu_extdatatool 3DS HomeMenu extdata Tool]
| Tool for accessing the SD extdata which Home Menu uses. This essentially allows writing custom themes to extdata which get loaded at Home Menu startup.
| [[User:yellows8|yellows8]]
| [https://github.com/yellows8/3ds_homemenu_extdatatool/releases]
| Yes
|
|-
| [https://github.com/markwinap/3DS_Nyan_Cat 3DS Nyan Cat]
| 3DS Nyan Cat using LIBSF2D.
| [[User:markwinap|markwinap]]
| [https://www.dropbox.com/s/e400my3xm0zw74r/nyan_cat.zip?dl=0 Here]
| Yes
|
|-
| [https://gbatemp.net/threads/videahs-various-stuff.397562/ 3dsfetch]
| Small 3DS version of a popular Linux ricing script called screenfetch
| [[User:VideahGams|VideahGams]]
| [https://github.com/VideahGams/3dsfetch Here]
| [https://github.com/VideahGams/3dsfetch Yes]
|
|-
| [https://github.com/S3r1alpari4h/Brainfudge3DS Brainfudge]
| Alpha brainfuck interpreter
| [[User:s3r1alpari4h|V0idst4r]]
| [https://github.com/s3r1alpari4h/Brainfudge3DS/releases/ Here]
| [https://github.com/S3r1alpari4h/Brainfudge3DS Yes]
|
|-
| [https://github.com/plutooo/ctrrpc ctrrpc]
| A small and easily extensible RPC server/client written in C/Python. Allows you to quickly poke service-commands and syscalls over wifi from a Python shell on your PC. Useful during reverse-engineering.
| [[User:plutooo|plutoo]]
| N/A
| Yes
|
|-
| [https://github.com/yellows8/ctr-streaming-server ctr-streaming-server]
| This is a server which runs on a 3DS, which receives audio/video for playback. This can also send [[HID_Shared_Memory|HID]] state to the client (see the README) when enabled. The included parse_hidstream tool can be used to parse that HID data to simulate keyboard/mouse input events, via Linux uinput.
| [[User:yellows8|yellows8]]
| N/A
| Yes
|
|-
| [https://github.com/Rinnegatamante/CHMM2 Custom Home Menu Manager 2]
| Theme manager for Nintendo 3DS
| [[User:Rinnegatamante|Rinnegatamante]]
| [http://rinnegatamante.it/CHMM2.rar Here]
| Yes
|
|-
| [https://github.com/DownloadMii/DownloadMii DownloadMii]
| This is a WIP homebrew online store.
| [[User:filfat|filfat]]
| [https://www.downloadmii.com/download/#release Latest]
| Yes
|
|-
| [https://github.com/linoma/fb43ds fb43ds]
| This is a simple Facebook's chat client
| [[User:linoma|linoma]]
| [https://github.com/linoma/fb43ds Here]
| Yes
|
|-
| [https://github.com/Steveice10/FBI FBI]
| Open source CIA (un)installer.
| [[User:Steveice10|Steveice10]]
| [https://github.com/Steveice10/FBI/releases/ Here]
| Yes
|
|-
| [https://github.com/iamevn/for-anyone-who-walks-a-lot for-anyone-who-walks-a-lot]
| Tool to get past the 10 coin per day limit on earning Play Coins by walking.
| [[User:iamevn|iamevn]]
| [https://github.com/iamevn/for-anyone-who-walks-a-lot/releases Here]
| Yes
|
|-
| [https://github.com/mtheall/ftbrony ftBRONY]
| An FTP server.
| [[User:mtheall|mtheall]]
| [https://github.com/mtheall/ftbrony/releases Here]
| Yes
|
|-
| [https://github.com/iamevn/FTP-3DS FTP-3DS]
| Fork of ftBRONY with a Nintendo theme.
| [[User:iamevn|iamevn]]
| [https://github.com/iamevn/FTP-3DS/releases Here]
| Yes
|
|-
| [https://github.com/smealum/ftPONY ftPONY]
| A basic FTP server, useful for testing new homebrew versions without swapping the SD card.
| [[User:smea|smea]]
| [https://mega.co.nz/#!nchBkL7B!T3vXnX4q8Uwp6APYYTDSZi2bkm25la-Qyz6j4CjsllI Here]
| Yes
|
|-
| [https://github.com/zeta0134/3ds-homebrew-browser Homebrew Browser]
| Download homebrew from the internet!
| [[User:cromo|cromo]] [[User:zeta0134|zeta0134]]
| [https://github.com/zeta0134/3ds-homebrew-browser/releases/tag/v0.1 Here]
| Yes
|
|-
|[https://github.com/meladroit/svdt svdt]
|Save Data Explorer/Manager
|[[User:meladroit|meladroit]]
|[https://github.com/meladroit/svdt/releases Here]
|Yes
|
|}

===Game Engines===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
! width="10%" | Last Updated
|-
| [https://gbatemp.net/threads/release-l%C3%B6vepotion-l%C3%96ve-api-for-3ds-homebrew-beta.397559/ LövePotion]
| An unofficial work in progress implementation of the LÖVE API for 3DS Homebrew
| [[User:VideahGams|VideahGams]]
| [https://github.com/VideahGams/LovePotion/releases Here]
| [https://github.com/VideahGams/LovePotion Yes]
|
|}

===Games===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
! width="10%" | Last Updated
|-
| [http://gbatemp.net/threads/release-100-boxes-2ds.384714/ 100 Boxes 2DS]
| Simple puzzle game.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/100Boxes2DS/100_Boxes_2DS.rar Here]
| Yes
|
|-
| [https://github.com/MrJPGames/2048-3D 2048-3D]
| "2048 was a big hit not so long ago, and I still see many people at my school playing it. So I thought it would be pretty cool to be able to play 2048 on the go on the 3DS."
| [[User:MrJPGames|Jasper Peters]]
| [https://github.com/MrJPGames/2048-3D/blob/master/2048-3D.3dsx?raw=true Here]
| Yes
|
|-
| [https://github.com/smealum/3dscraft 3DSCraft]
| Minecraft clone.
| [https://twitter.com/smealum smea]
| [http://smealum.github.io/3dscraft/downloads/3dscraft_141120.zip Here]
| Yes
|
|-
| [https://gbatemp.net/threads/preview-ld-34-port-antibounce.406361 Antibounce]
| Move your player to bounce around and collect coins. Go between screens through the holes in the sides of the floor. 3D can also be enabled.
| TurtleP
| [https://github.com/TurtleP/Antibounce/releases Here]
| [https://github.com/TurtleP/Antibounce Yes]
|
|-
| [https://github.com/UnsureSherlock/checkers3ds/tree/master checkers3ds]
| A buggy ASCII checkers game
| [[User:UnsureSherlock|UnsureSherlock]]
| [http://www.filedropper.com/checkers3ds Here]
| Yes
|
|-
| [https://gbatemp.net/threads/release-drawattack-networked-drawing-game.402291/ DrawAttack]
| Online multiplayer drawing game like pictionary.
| [[User:Cruel|Cruel]]
| [https://github.com/Cruel/DrawAttack/releases/latest Here]
| [https://github.com/Cruel/DrawAttack Yes]
| 11/16/15
|-
| [http://gbatemp.net/threads/release-hamsters-2ds.383457/ Hamsters 2DS]
| A hamster breeding game in text mode.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/Hamsters2DS/Hamsters_2DS.rar Here]
| No
|
|-
| [https://github.com/BHSPitMonkey/Helii3DS Helii]
| Fly a helicopter through a 2D tunnel! Ported from the Wii.
| [[User:BHSPitMonkey|BHSPitMonkey]]
| [https://github.com/BHSPitMonkey/Helii3DS/releases/ Here]
| [https://github.com/BHSPitMonkey/Helii3DS Yes]
| 9/18/15
|-
| [http://gowengamedev.com/insectoid-defense/ Insectoid Defense]
| A Sci-Fi Tower Defense game. This is merely a port of the Android/iOS/Windows Phone version.
| [http://www.3dbrew.org/wiki/User:Sgowen sgowen]
| [https://github.com/GowenGameDevOpenSource/insectoid-defense/releases/download/v1.0-all/insectoid-defense-3DS.zip Here]
| [https://github.com/GowenGameDevOpenSource/insectoid-defense Yes]
|
|-
| [https://gbatemp.net/threads/videahs-various-stuff.397562/ NumberFucker3DS]
| Simple math game, originally used as a debug game for LövePotion
| [[User:VideahGams|VideahGams]]
| [https://github.com/VideahGams/NumberFucker3DS Here]
| [https://github.com/VideahGams/NumberFucker3DS Yes]
|
|-
| [https://gbatemp.net/threads/release-mastermind-3ds.394710/#post-5611660 Mastermind 3DS]
| Mastermind on 3DS
| [[User:MrJPGames|Jasper Peters]]
| [https://github.com/MrJPGames/Mastermind-3DS/blob/master/Mastermind.zip?raw=true Here]
| Yes
|
|-
| [http://gbatemp.net/threads/release-minesweeper-2ds.384185/ Minesweeper 2DS]
| Minesweeper clone.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/Minesweeper2DS/Minesweeper_2DS.rar Here]
| Yes
|
|-
| [http://gbatemp.net/threads/release-paddle-puffle-3ds.392215/ Paddle Puffle 3DS]
| A port of [http://puffles.gatuno.mx Paddle Puffle] for the 3DS.
| Peanut42
| [http://puffles.gatuno.mx/releases/paddlepuffle3ds.zip Here]
| [https://github.com/gatuno/PaddlePuffle3DS Yes]
|
|-
| [http://gbatemp.net/threads/release-pixel-shuffle-2ds.398540/ Pixel Shuffle 2DS]
| Puzzle game.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/PixelShuffle2DS/Pixel_Shuffle_2DS.rar Here]
| Yes
|
|-
| [http://gbatemp.net/threads/release-pixel-swap-2ds.395749/ Pixel Swap 2DS]
| Relaxing Puzzle game.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/PixelSwap2DS/Pixel_Swap_2DS.rar Here]
| Yes
|
|-
| [https://github.com/smealum/portal3DS Portal3DS]
| An adaptation of [https://en.wikipedia.org/wiki/Portal_(video_game) Portal] for the 3DS.
| [https://twitter.com/smealum smea]
| N/A
| [https://github.com/smealum/portal3DS Yes]
|
|-
| [https://gbatemp.net/threads/release-reversi-othello-for-3ds.395442/ Reversi]
| [https://en.wikipedia.org/wiki/Reversi Reversi] for the 3DS.
| [[User:MrJPGames|Jasper Peters]]
| [https://github.com/MrJPGames/Othello-3DS/releases Here]
| [https://github.com/MrJPGames/Othello-3DS Yes]
|
|-
| [https://gbatemp.net/threads/release-space-fruit.399088/ Space Fruit]
| Hackathon game by 4 friends ported to 3DS. Asteroids but with fruit (kinda)
| TurtleP
| [https://github.com/TurtleP/Space_Fruit/releases Here]
| [https://github.com/TurtleP/Space_Fruit/tree/3DS Yes]
|
|-
| [http://gowengamedev.com/tappy-plane/ Tappy Plane]
| A Flappy Bird clone, but with a colorful plane. This is merely a port of the Android/iOS/Windows Phone version.
| [http://www.3dbrew.org/wiki/User:Sgowen sgowen]
| [https://github.com/GowenGameDevOpenSource/tappy-plane/releases/download/v1.0-all/tappy-plane-3DS.zip Here]
| [https://github.com/GowenGameDevOpenSource/tappy-plane Yes]
|
|-
| [http://gbatemp.net/threads/release-tilemap-2ds.386733/ TileMap 2DS]
| Puzzle game.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/TileMap2DS/TileMap_2DS.rar Here]
| Yes
|
|-
| [http://gbatemp.net/threads/release-tiles-2ds.385796/ Tiles 2DS]
| Puzzle game, Lights Out Like.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/Tiles2DS/Tiles_2DS.rar Here]
| Yes
|
|-
| [http://gbatemp.net/threads/trucmuche-2ds-09.404859// Trucmuche 2DS 09]
| Hidden Objects.
| [[User:Cid2mizard|Cid2mizard]]
| [http://3ds.nintendomax.com/Homebrews/Jeux/Trucmuche2DS09/Trucmuche_2DS_09.rar Here]
| Yes
|
|-
| [https://github.com/Steveice10/WorldOf3DSand World of 3DSand]
| World of Sand clone.
| [[User:Steveice10|Steveice10]]
| [https://github.com/Steveice10/WorldOf3DSand/releases/ Here]
| Yes
|
|-
| [https://github.com/smealum/yeti3DS Yeti3DS]
| A quick and dirty port of Derek Evans' Yeti3D software rendering engine.
| [https://twitter.com/smealum smea]
| N/A
| Yes
|
|-
| [https://github.com/masterfeizz/ctrQuake ctrQuake]
| Unofficial port of Quake for the 3DS, fully playable.
| [https://twitter.com/masterfeizz MasterFeizz]
| [https://github.com/masterfeizz/ctrQuake/releases/ Here]
| Yes
|
|-
| [https://github.com/masterfeizz/EDuke3D EDuke3D]
| Unofficial port of EDuke32 for the Nintendo 3DS
| [https://twitter.com/masterfeizz MasterFeizz]
| [https://github.com/masterfeizz/EDuke3D/releases/ Here]
| Yes
|
|}

===Emulators===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
! width="10%" | Last Updated
|-
| [https://github.com/st4rk/3DNES 3DNES]
| An NES emulator. (No longer being worked on)
| St4rk
| [http://filetrip.net/3ds-downloads/homebrew/dl-3dnes-1-2-f32931.html Here]
| Yes
| March 2015
|-
| [https://github.com/StapleButter/blargSnes blargSnes]
| A Super Nintendo emulator. A compatibility list can be found [http://wiki.gbatemp.net/wiki/BlargSnes_Compatibility_List here].
| StapleButter
| [http://kuribo64.net/get.php?id=fYRTHLeS0pR3DXFw Here]
| Yes
| May 2015
|-
| [https://github.com/xerpi/CHIP-3DS CHIP-3DS]
| A simple and slow CHIP-8 emulator.
| xerpi
| [https://www.mediafire.com/?y94yjhzf70fsfsi Here]
| Yes
| March 2015
|-
| [https://github.com/shinyquagsire23/gpsp CitrAGB]
| Yet another GBA emulator.
| shinyquagsire23
| [https://www.dropbox.com/s/sxb7x34u58g4zo2/3ds.3dsx?dl=0 Here]
| Yes
| September 2015
|-
| [https://github.com/Steveice10/GameYob/ GameYob]
| A Game Boy (Color) emulator. A compatibility list can be found [http://wiki.gbatemp.net/wiki/GameYob_3DS_Compatibility_List here].
| Drenn/Steveice10
| [https://github.com/Steveice10/GameYob/releases Here]
| Yes
| November 2015
|-
| [https://github.com/mrdanielps/r3Ddragon r3Ddragon]
| A virtual boy emulator.
| mrdanielps
| [https://github.com/mrdanielps/r3Ddragon/releases/download/v0.85-preview.1/r3Ddragon.cia Here]
| Yes
| October 2015
|-
| [https://github.com/libretro/RetroArch RetroArch]
| A multisystem emulator. (GB, GBA, SNES, Genesis, CPS1, CPS2, etc.)
| libretro
| [http://buildbot.libretro.com/nightly/nintendo/3ds/ Here]
| Yes
| December 2015
|-
| [https://github.com/mgba-emu/mgba mGBA]
| A GBA emulator that runs good without kernel hax.
| endrift
| [https://mgba.io/nightlies.html Here]
| Yes
| December 2015
|}

===Icon Packs===
Icon Packs are SMDH Packs for homebrew apps
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Last Updated
|-
|Simplok
|The first 3DS Icon pack.
|link6155
|[http://1drv.ms/1EJCq2e Download]
| 7 September 2015
|-
|1LP
|Cool Icon Pack!.
|[[User:100pcrack|100pcrack]]
|[http://github.com/100pcrack/1LP/releases Releases]
| 27 November 2015
|}

===Demos===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
! width="10%" | Last Updated
|-
| cubedemo
| A short demo of Homebrew on 3ds with working sound.
| [[User:plutoo|plutoo]]
| [https://mega.co.nz/#!KUQFiQYA!pv8HDEyrmuX6Eyw2hW0opL7gf9Ztmjd9J5pPsvs_rD4 Here]
| No
|
|-
| Spine 2D
| Demo of [http://esotericsoftware.com/ Spine] 2D skeletal animations
| [[User:Cruel|Cruel]]
| [https://mega.nz/#!Xg411B5R!kcVHP69Ilggmjh4q5OYmr2cFvf5UGdHWA98-_VttDTo 3DSX] [https://mega.nz/#!z8gxHSQb!H0as1A4wqYrdKBhXJwdYik7nPd_msXJhz5N1CeZm1Iw CIA]
| No
|
|}
===Alternate Launchers===
{| class="wikitable" border="1"
! width="20%" | Name
! width="50%" | Description
! width="10%" | Author
! width="10%" | Download
! width="10%" | Open-Source
|-
| Mashers HBL
| Homebrew Launcher with a grid and folders support.
| [[User:Mashers|Mashers]]
| [http://gbatemp.net/threads/release-homebrew-launcher-with-grid-layout.397527/ Here]
| No
|}

SOCU:poll

2014-12-08T20:39:07Z

Mtheall: /* Events */

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x00140084]
|-
| 1
| nfds_t nfds
|-
| 2
| int timeout
|-
| 3
| Value 0x20 (processID header)
|-
| 4
| ProcessID set by the ARM11 kernel.
|-
| 5
| (insize<<14) <nowiki>|</nowiki> 0x2802
|-
| 6
| Pointer to input pollfd struct array
|}

The following is located 0x100-bytes after the beginning of the above command buffer:
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| (outsize<<14) <nowiki>|</nowiki> 2
|-
| 1
| Pointer to output pollfd struct array
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code
|-
| 1
| Result code
|-
| 2
| POSIX return value
|}

=pollfd struct=
{| class="wikitable" border="1"
|-
! Type
! Name
! Description
|-
| u32
| fd
| Socket handle
|-
| u32
| events
| Events to poll for (input)
|-
| u32
| revents
| Events received (output)
|}

=Events=
Events are a bitwise set of these flags.
{| class="wikitable" border="1"
|-
! Value
! Name
! Input/Output
! Description
|-
| 0x01
| POLLIN
| Both
| Can recv() data from socket without blocking. For listen sockets, this means you can accept() a connection without blocking.
|-
| 0x02
| POLLPRI
| Both
| There is OOB data ready to recv(). Appears that recv()'ing without OOB flag still reads OOB data?
|-
| 0x04
| ???
| ???
| Have never seen this flag. Could possibly be POLLHUP (need to test).
|-
| 0x08
| POLLERR
| Out
| Socket has an error condition.
|-
| 0x10
| POLLOUT
| Both
| Can send() data to socket without blocking. For a non-blocking connect(), this means the connection has completed (need to test).
|-
| 0x20
| POLLNVAL
| Out
| Invalid socket handle. This is set if you use fd=-1, which is non-standard behavior.
|-
| ???
| POLLHUP
| Out
| Socket has been disconnected.
|}

SOCU:poll

2014-12-08T17:04:46Z

Mtheall:

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x00140084]
|-
| 1
| nfds_t nfds
|-
| 2
| int timeout
|-
| 3
| Value 0x20 (processID header)
|-
| 4
| ProcessID set by the ARM11 kernel.
|-
| 5
| (insize<<14) <nowiki>|</nowiki> 0x2802
|-
| 6
| Pointer to input pollfd struct array
|}

The following is located 0x100-bytes after the beginning of the above command buffer:
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| (outsize<<14) <nowiki>|</nowiki> 2
|-
| 1
| Pointer to output pollfd struct array
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code
|-
| 1
| Result code
|-
| 2
| POSIX return value
|}

=pollfd struct=
{| class="wikitable" border="1"
|-
! Type
! Name
! Description
|-
| u32
| fd
| Socket handle
|-
| u32
| events
| Events to poll for (input)
|-
| u32
| revents
| Events received (output)
|}

=Events=
Events are a bitwise set of these flags.
{| class="wikitable" border="1"
|-
! Value
! Name
! Input/Output
! Description
|-
| 0x01
| POLLIN
| Both
| Can recv() data from socket without blocking. For listen sockets, this means you can accept() a connection without blocking.
|-
| 0x02
| POLLPRI
| Both
| There is OOB data ready to recv(). Appears that recv()'ing without OOB flag still reads OOB data?
|-
| 0x04
| ???
| ???
| Have never seen this flag. Could possibly be POLLHUP (need to test).
|-
| 0x08
| ???
| ???
| This flag is almost always set when requested.
|-
| 0x10
| POLLOUT
| Both
| Can send() data to socket without blocking. For a non-blocking connect(), this means the connection has completed (need to test).
|-
| 0x20
| POLLNVAL
| Out
| Invalid socket handle. This is set if you use fd=-1, which is non-standard behavior.
|-
| ???
| POLLERR
| Out
| Socket error.
|-
| ???
| POLLHUP
| Out
| Socket has been disconnected.
|}

Homebrew Applications

2014-12-05T00:11:07Z

Mtheall:

==Installing==
Applications are installed by copying the necessary files to the 3ds/ folder in the root of the SD-card. Most applications come with two files:
* boot.3dsx: The executable.
* icon.bin: The icon/metadata.

The [[Homebrew Launcher]] will scan the sdcard for all .3dsx files, but will only display an icon for those who have one according to the format described above.

==List==
{| class="wikitable" border="1"
! Category
! Name
! Description
! Author
! Download
! Open-Source
|-
| Demo
| cubedemo
|
| [[User:plutoo|plutoo]]
| [https://mega.co.nz/#!KUQFiQYA!pv8HDEyrmuX6Eyw2hW0opL7gf9Ztmjd9J5pPsvs_rD4 Here]
| No
|-
| Game
| [https://github.com/smealum/yeti3DS Yeti3DS]
| A quick and dirty port of Derek Evans' Yeti3D software rendering engine.
| [[User:smea|smea]]
| N/A
| Yes
|-
| Game
| [https://github.com/smealum/3dscraft 3DSCraft]
| Minecraft clone.
| [[User:smea|smea]]
| N/A
| Yes
|-
| Game
| [https://github.com/Steveice10/WorldOf3DSand World of 3DSand]
| World of Sand clone.
| [[User:Steveice10|Steveice10]]
| [https://www.dropbox.com/s/91tqtydxpny9p1g/WorldOf3DSand.zip?dl=0 Here]
| Yes
|-
| Emulator
| [https://github.com/StapleButter/blargSnes blargSnes]
| A Super Nintendo emulator.
| StapleButter
| [http://blargsnes.kuribo64.net/download/blargSnes_1.2.zip Here]
| Yes
|-
| Emulator
| [https://github.com/Drenn1/GameYob/tree/master/platform/3ds GameYob]
| A Game Boy (Color) emulator.
| Drenn
| [https://dl.dropboxusercontent.com/u/100702766/gameyob/gameyob_3ds.zip Here]
| Yes
|-
| Emulator
| [https://github.com/st4rk/3DNES 3DNES]
| An NES emulator.
| St4rk
| N/A
| Yes
|-
|-
| Emulator
| [https://github.com/xerpi/CHIP-3DS CHIP-3DS]
| A simple and slow CHIP-8 emulator.
| xerpi
| [https://www.mediafire.com/?y94yjhzf70fsfsi Here]
| Yes
|-
| Application
| [https://github.com/smealum/ftPONY ftPONY]
| A basic FTP server, useful for testing new homebrew versions without swapping the SD card.
| [[User:smea|smea]]
| [https://mega.co.nz/#!nchBkL7B!T3vXnX4q8Uwp6APYYTDSZi2bkm25la-Qyz6j4CjsllI Here]
| Yes
|-
| Application
| [https://github.com/mtheall/ftbrony ftBRONY]
| An FTP server.
| [[User:mtheall|mtheall]]
| N/A
| Yes
|-
| Application
| [https://github.com/plutooo/ctrrpc ctrrpc]
| A small and easily extensible RPC server/client written in C/Python. Allows you to quickly poke service-commands and syscalls over wifi from a Python shell on your PC. Useful during reverse-engineering.
| [[User:plutooo|plutoo]]
| N/A
| Yes
|-
| Application
| [https://github.com/yellows8/ctr-streaming-server ctr-streaming-server]
| This is a server which runs on a 3DS, which receives audio/video for playback. This can also send [[HID_Shared_Memory|HID]] state to the client (see the README) when enabled. The included parse_hidstream tool can be used to parse that HID data to simulate keyboard/mouse input events, via Linux uinput.
| [[User:yellows8|yellows8]]
| N/A
| Yes
|}

FS:IsSdmcWritable

2014-08-26T20:56:34Z

Mtheall: Created page with "=Request= {| class="wikitable" border="1" |- ! Index Word ! Description |- | 0 | Header code [0x08180000] |} =Response= {| class="wikitable" border="1" |- ! Index Word ! Des..."

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x08180000]
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code
|-
| 1
| Result code
|-
| 2
| Whether SD is writable
|}

FS:IsSdmcDetected

2014-08-26T20:55:42Z

Mtheall: Created page with "=Request= {| class="wikitable" border="1" |- ! Index Word ! Description |- | 0 | Header code [0x08170000] |} =Response= {| class="wikitable" border="1" |- ! Index Word ! Des..."

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x08170000]
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code
|-
| 1
| Result code
|-
| 2
| Whether SD is detected
|}

Filesystem services

2014-08-26T20:49:50Z

Mtheall: /* Filesystem service "fs:USER" */

[[Category:Services]]

= Filesystem service "fs:USER" =
{| class="wikitable" border="1"
|-
! Command Header
! Available since system version
! Description
! scope="col" width="400" | Required [[NCCH/Extended_Header|exheader]] accessinfo bitmask
|-
| 0x000100C6
|
| Dummy1
| None
|-
| 0x040100C4
|
| Control
| None
|-
| 0x08010002
|
| [[FS:Initialize|Initialize]]
| None
|-
| 0x080201C2
|
| [[FS:OpenFile|OpenFile]]
| None
|-
| 0x08030204
|
| [[FS:OpenFileDirectly|OpenFileDirectly]]
| None
|-
| 0x08040142
|
| [[FS:DeleteFile|DeleteFile]]
| None
|-
| 0x08050244
|
| RenameFile
| None
|-
| 0x08060142
|
| DeleteDirectory
| None
|-
| 0x08070142
|
| DeleteDirectoryRecursively
| None
|-
| 0x08080202
|
| CreateFile
| None
|-
| 0x08090182
|
| [[FS:CreateDirectory|CreateDirectory]]
| None
|-
| 0x080A0244
|
| RenameDirectory
| None
|-
| 0x080B0102
|
| [[FS:OpenDirectory|OpenDirectory]]
| None
|-
| 0x080C00C2
|
| [[FS:OpenArchive|OpenArchive]]
| Each archive idcode has separate accessinfo bitmasks, if any.
|-
| 0x080D0144
|
| ControlArchive
| None
|-
| 0x080E0080
|
| [[FS:CloseArchive|CloseArchive]]
| None
|-
| 0x080F0180
|
| FormatThisUserSaveData
| None
|-
| 0x08100200
|
| CreateSystemSaveData
| 0x4, for when the input saveID doesn't match the exheader saveID.
|-
| 0x08110040
|
| DeleteSystemSaveData
| 0x1004, for when the input saveID doesn't match the exheader saveID.
|-
| 0x08120080
|
| GetFreeBytes
| None
|-
| 0x08130000
|
| GetCardType
| 0x1017
|-
| 0x08140000
|
| [[FS:GetSdmcArchiveResource|GetSdmcArchiveResource]]
| None
|-
| 0x08150000
|
| [[FS:GetNandArchiveResource|GetNandArchiveResource]]
| None
|-
| 0x08160000
|
| GetSdmcFatfsError
| 0x2
|-
| 0x08170000
|
| [[FS:IsSdmcDetected|IsSdmcDetected]]
| None
|-
| 0x08180000
|
| [[FS:IsSdmcWritable|IsSdmcWritable]]
| None
|-
| 0x08190042
|
| GetSdmcCid
| 0x2
|-
| 0x081A0042
|
| GetNandCid
| 0x2
|-
| 0x081B0000
|
| GetSdmcSpeedInfo
| 0x2
|-
| 0x081C0000
|
| GetNandSpeedInfo
| 0x2
|-
| 0x081D0042
|
| GetSdmcLog
| 0x2
|-
| 0x081E0042
|
| GetNandLog
| 0x2
|-
| 0x081F0000
|
| ClearSdmcLog
| 0x2
|-
| 0x08200000
|
| ClearNandLog
| 0x2
|-
| 0x08210000
|
| CardSlotIsInserted
| 0x1017
|-
| 0x08220000
|
| CardSlotPowerOn
| 0x2
|-
| 0x08230000
|
| CardSlotPowerOff
| 0x2
|-
| 0x08240000
|
| CardSlotGetCardIFPowerStatus
| 0x2
|-
| 0x08250040
|
| CardNorDirectCommand
| 0x2
|-
| 0x08260080
|
| CardNorDirectCommandWithAddress
| 0x2
|-
| 0x08270082
|
| CardNorDirectRead
| 0x2
|-
| 0x082800C2
|
| CardNorDirectReadWithAddress
| 0x2
|-
| 0x08290082
|
| CardNorDirectWrite
| 0x2
|-
| 0x082A00C2
|
| CardNorDirectWriteWithAddress
| 0x2
|-
| 0x082B00C2
|
| CardNorDirectRead_4xIO
| 0x2
|-
| 0x082C0082
|
| CardNorDirectCpuWriteWithoutVerify
| 0x2
|-
| 0x082D0040
|
| CardNorDirectSectorEraseWithoutVerify
| 0x2
|-
| 0x082E0040
|
| [[FS:GetProductInfo|GetProductInfo]]
| 0x1005
|-
| 0x082F0040
|
| [[FS:GetProgramLaunchInfo|GetProgramLaunchInfo]]
| 0x1005
|-
| 0x08300182
|
| CreateExtSaveData
| 0xC, for when the input extdataID doesn't match the exheader extdataID.
|-
| 0x08310180
|
| CreateSharedExtSaveData
| 0x1005
|-
| 0x08320102
|
| [[FS:ReadExtSaveDataIcon|ReadExtSaveDataIcon]]
| 0x100D, for when the input extdataID doesn't match the exheader extdataID.
|-
| 0x08330082
|
| EnumerateExtSaveData
| 0x1005
|-
| 0x08340082
|
| EnumerateSharedExtSaveData
| 0x1005
|-
| 0x08350080
|
| DeleteExtSaveData
| 0x100D, for when the input extdataID doesn't match the exheader extdataID.
|-
| 0x08360080
|
| DeleteSharedExtSaveData
| 0x1005
|-
| 0x08370040
|
| SetCardSpiBaudRate
| 0x2
|-
| 0x08380040
|
| SetCardSpiBusMode
| 0x2
|-
| 0x08390000
|
| SendInitializeInfoTo9
| None
|-
| 0x083A0100
|
| GetSpecialContentIndex
| 0x1005
|-
| 0x083B00C2
|
| GetLegacyRomHeader
| 0x1015
|-
| 0x083C00C2
|
| GetLegacyBannerData
| 0x1015
|-
| 0x083D0100
|
| CheckAuthorityToAccessExtSaveData
| 0x44
|-
| 0x083E00C2
|
| QueryTotalQuotaSize
| None
|-
| 0x083F00C0
|
| GetExtDataBlockSize
| None
|-
| 0x08400040
|
| AbnegateAccessRight
|
|-
| 0x08410000
|
| DeleteSdmcRoot
| 0x1005
|-
| 0x08420040
|
| DeleteAllExtSaveDataOnNand
| 0x1005
|-
| 0x08430000
|
| [[FS:InitializeCtrFileSystem|InitializeCtrFileSystem]]
| None
|-
| 0x08440000
|
| CreateSeed
| 0x2
|-
| 0x084500C2
|
| GetFormatInfo
| ?
|-
| 0x08460102
|
| GetLegacyRomHeader2
| 0x1015
|-
| 0x08470180
|
| FormatCtrCardUserSaveData
| 0x6
|-
| 0x08480042
|
| GetSdmcCtrRootPath
| 0x100D
|-
| 0x08490040
|
| GetArchiveResource
| ?
|-
| 0x084A0002
|
| ExportIntegrityVerificationSeed
| 0x4000
|-
| 0x084B0002
|
| ImportIntegrityVerificationSeed
| 0x4000
|-
| 0x084C0242
|
| FormatSaveData
| 0x6, in some cases this right isn't needed however.
|-
| 0x084D0102
|
| GetLegacySubBannerData
| 0x1015
|-
| 0x084E0342
|
| [[FS:UpdateSha256Context|UpdateSha256Context]]
| 0x5
|-
| 0x084F0102
|
| ReadSpecialFile
| None
|-
| 0x08500040
|
| GetSpecialFileSize
| None
|-
| 0x08510242
| [[3.0.0-5]]
| CreateExtSaveData
| Shared extdata: 0x101005. Regular extdata in certain cases: 0xC.
|-
| 0x08520100
| [[3.0.0-5]]
| DeleteExtSaveData (u32 flags, u64 extdataID)
| Shared extdata: 0x101005. Regular extdata in certain cases: 0x10100D.
|-
| 0x08530142
| [[3.0.0-5]]
| ReadExtSaveDataIcon
| 0x10100D(this doesn't apply in certain cases however)
|-
| 0x085400C0
| [[3.0.0-5]]
| GetExtDataBlockSize?
| 0x10100D(this doesn't apply in certain cases however)
|-
| 0x08550102
| [[3.0.0-5]]
| EnumerateExtSaveData
| 0x101005
|-
| 0x08560200
| [[3.0.0-5]]
| FsCreateSystemSaveData?
| 0x4(this doesn't apply in certain cases however)
|-
| 0x08570080
| [[3.0.0-5]]
| DeleteSystemSaveData
| 0x1004(this doesn't apply in certain cases however)
|-
| 0x08580000
| [[3.0.0-5]]
| [[FS:GetMovableSedHashedKeyYRandomData|GetMovableSedHashedKeyYRandomData]]
| 0x2004
|-
| 0x08590200
| [[3.0.0-5]]
| SetMovableSedHashedKeyYRandomData?
| 0x2004
|-
| 0x085A00C0
| [[3.0.0-5]]
| SetArchivePriority(u64 ID,u32 priority)
| None
|-
| 0x085B0080
| [[3.0.0-5]]
| GetArchivePriority(u64 ID,u32 *priority)
| None
|-
| 0x085C00C0
| [[3.0.0-5]]
| ?
| 0xE
|-
| 0x085D0180
| [[3.0.0-5]]
| ?
| 0x100001
|-
| 0x085E0040
| [[3.0.0-5]]
| ?
| 0xE
|-
| 0x085F0040
| [[3.0.0-5]]
| ?
| 0x12004
|-
| 0x08600042
| [[3.0.0-5]]
| EnumerateSystemSaveData
| 0x2004
|-
| 0x08610042
| [[3.0.0-5]]
| InitializeWithSdkVersion
| None
|-
| 0x08620040
| [[3.0.0-5]]
| SetPriority
| None
|-
| 0x08630000
| [[3.0.0-5]]
| GetPriority
| None
|-
| 0x08640000
| [[3.0.0-5]]
| Stubbed, this returns an error.
| None
|-
| 0x08650140
| [[4.0.0-7]]
| Unknown, this is used with [[Anti Savegame Restore]].
| 0x121004(in certain cases this doesn't apply however)
|-
| 0x086600C0
| [[4.0.0-7]]
| Unknown, this is used with [[Anti Savegame Restore]].
| 0x121004(in certain cases this doesn't apply however)
|-
| 0x086700C4
| [[4.0.0-7]]
| ?
| 0x121004
|-
| 0x08680000
| [[4.0.0-7]]
| This loads the u8 mediatype for the current application from already initialized state, this u8 was originally loaded from the same data used by [[FS:GetProgramLaunchInfo|GetProgramLaunchInfo]]. This then writes the u8 to response-word[2]. This is used with [[Anti Savegame Restore]].
| None
|-
| 0x08690000
| [[4.0.0-7]]
| Stubbed, this returns an error.
| None
|-
| 0x086A0082
| [[4.0.0-7]]
| This is a wrapper for [[Filesystem_services_PXI|FSPXI]] command 0x00550082.
| None
|-
| 0x086B00C2
| ?
| ?
| 00121004
|-
| 0x086C00C2
| ?
| ?
| 00121004
|-
| 0x086D0040
| ?
| ?
| 00020004
|-
| 0x086E00C0
| ?
| ?
| ?None?
|-
| 0x086F0040
| ?
| ?
| 0xE
|-
| 0x087000C2
| ?
| ?
| ?None?
|-
| 0x08710100
| ?
| ?
| 0xC
|-
| 0x087201C0
| ?
| ?
| 00080004
|-
| 0x087300C0
| ?
| ?
| 00080004
|-
| 0x08740000
| ?
| ?
| 00080004
|-
| 0x08750140
| ?
| ?
| ?None?
|-
| 0x087600C0
| ?
| ?
| ?None?
|-
| 0x08770100
| ?
| ?
| ?
|-
| 0x087800C0
| ?
| ?
| ?
|}

When access rights are required for a command, at least one of the bits in the process accessinfo specified in the above table for the command must be set. Error 0xD9004676 is returned when a process attempts to use a command which it doesn't have access rights for the command. The exheader accessinfo field is all-zero for most applications. Note that the permissions listed in the above table is for system-version v2.x, therefore permission bit(s) added with newer FIRM may be missing from this.

Each session for fs:USER has separate permissions, initially these are set to all-zero for new fs:USER sessions. The permissions/etc for fs:USER sessions are initialized via [[FS:Initialize]](loaded from the user process exheader).

=File service=
{| class="wikitable" border="1"
|-
! Command Header
! Description
|-
| 0x000100C6
| Dummy1
|-
| 0x040100C4
| Control
|-
| 0x08010100
| OpenSubFile
|-
| 0x080200C2
| [[FSFile:Read|Read]]
|-
| 0x08030102
| [[FSFile:Write|Write]]
|-
| 0x08040000
| [[FSFile:GetSize|GetSize]]
|-
| 0x08050080
| [[FSFile:SetSize|SetSize]]
|-
| 0x08060000
| GetAttributes
|-
| 0x08070040
| SetAttributes
|-
| 0x08080000
| [[FSFile:Close|Close]]
|-
| 0x08090000
| Flush
|-
| 0x080A0040
| SetPriority
|-
| 0x080B0000
| GetPriority?
|-
| 0x080C0000
| OpenLinkFile
|}

=Directory service=
{| class="wikitable" border="1"
|-
! Command Header
! Description
|-
| 0x000100C6
| Dummy1
|-
| 0x040100C4
| Control
|-
| 0x08010042
| [[FSDir:Read|Read]]
|-
| 0x08020000
| [[FSDir:Close|Close]]
|}

= Filesystem service "fs:LDR" =
This service is identical to fs:USER, except [[FS:OpenArchive]] archive 0x2345678E can only be accessed with fs:LDR.

= ProgramRegistry service "fs:REG" =
{| class="wikitable" border="1"
|-
! Command Header
! Description
|-
| 0x000100C6
| Dummy1
|-
| 0x040103C0
| Register
|-
| 0x04020040
| Unregister
|-
| 0x040300C0
| GetProgramInfo
|-
| 0x04040100
| LoadProgram
|-
| 0x04050080
| UnloadProgram
|-
| 0x04060080
| CheckHostLoadId
|}

=Errors=
See [[Filesystem_services_PXI]].

FSDir:Read

2014-08-25T22:24:08Z

Mtheall: Update Entry Format

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x08010042]
|-
| 1
| Entrycount, number of entries to read.
|-
| 2
| ((entrycount*0x228)<<4) <nowiki>|</nowiki> 12;
|-
| 3
| Entry receive ptr
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code
|-
| 1
| Result code
|-
| 2
| Actually read entrycount
|}

=Entry format=
Below are the values that have been identified so far. There are unknown values from 0x219 to 0x227. The values following the entry name up to 0x20C appear to be untouched by the system.
{| class="wikitable" border="1"
|-
! Byte offset
! Description
|-
| 0x000
| Entry name (UTF-16, null-terminated)
|-
| 0x20C
| 8.3 file name (8 characters, 'longfilename' -> 'LONGFI~1')
|-
| 0x215
| unknown (observed values: 0x0A, 0x70, 0xFD)
|-
| 0x216
| 8.3 file extension (3 characters, set to spaces for directories)
|-
| 0x21A
| (byte) unknown (always 0x01)
|-
| 0x21B
| (byte) unknown (0x00 or 0x08)
|-
| 0x21C
| (byte) directory flag
|-
| 0x21D
| (byte) hidden flag
|-
| 0x21E
| (byte) archive flag
|-
| 0x21F
| (byte) read-only flag
|-
| 0x220
| (64-bit) file size (for files only)
|}

IPC

2014-08-21T18:31:52Z

Mtheall: x/y were swapped between header table and command structure table

Every IPC command sent to services starts with a u32 header code:
{| class="wikitable" border="1"
|-
! Bits
! Description
|-
| 0-5
| Number of translate parameters (=y)
|-
| 6-11
| Number of normal parameters (=x)
|-
| 12-15
| Unused
|-
| 16-31
| Command ID
|}

The entire command has the following structure:
{| class="wikitable" border="1"
|-
! Word
! Size
! Description
|-
| 0
| 1
| Header code
|-
| 1
| x
| Normal parameters
|-
| x
| y
| Translate parameters
|}

Translate parameters are modified/translated transparently by the kernel. They are used to transfer handles/buffers between the different processes.

The type of parameter is described by the bits 1-3 in the translation descriptor. Parameter types accepted for sending by the kernel are: 0, 1, 2, 5, 6, 7.
Type 0 is used to send handles across processes:
if desc & 0x30 == 0x20:
write process id to value
else:
translate handle
if desc & 0x30 == 0x10:
close handle for caller

For replies, only 0, 1, 5, 6, 7 are allowed. In other words any type 2 fields must be zeroed before calling svcReplyAndReceive on the server-side. For replies type 0, 1, 2 are ignored. Types 5, 6, 7 do something with the mem pointer upon reply. The type 0 descriptor can be used to ignore parameters. The number of parameters covered by a type-0 descriptor is (desc >> 26) + 1.

{| class="wikitable" border="1"
|-
! Type
! scope="col" width="150" | Usual form
! Description
|-
| 0
| 0x00000000
<handle>
| The corresponding value is a KHandle, that should be closed in calling process.
|-
| 0
| 0x00000010
<handle>
| The corresponding value is a KHandle, that will be duplicated.
|-
| 0
| 0x00000020
<placeholder>
| Let kernel set value to calling process ProcessID.
|-
| 1
| 0x0000???2 <nowiki>|</nowiki> (size<<14)
<ptr>
| The corresponding value contains a ptr to a buffer of said size, that should be copied to an already set-up buffer in destination process at threadlocalstorage+0x180.
|-
| 2
| 0x00000004
| Does something weird.
|-
| 3
| 0x00000006
| Does nothing?
|-
| 4
| 0x00000008
| This command will cause a kernelpanic.
|-
| 5
| <nowiki>0x0000000A | (size<<4)</nowiki>
<ptr>
| The corresponding value contains a ptr to a buffer of said size.
|-
| 6
| 0x0000000C <nowiki>|</nowiki> (size<<4)
<ptr>
| The corresponding value contains a ptr to a buffer of said size.
|-
| 7
| 0x0000000E <nowiki>|</nowiki> (size<<4)
<ptr>
| The corresponding value contains a ptr to a buffer of said size.
|}

Buffers from commands 5,6,7 will get mapped at virtual address 0x04000000+ in destination process.