3dbrew - User contributions [en]

SVC

2017-06-20T04:09:47Z

Yuriks: /* System calls */ Make ReplyAndReceive link to correct section in IPC page

= System calls =
'''Note: The argument-lists here apply to the official syscall wrapper-functions that are found in userland processes. The actual ordering passed to the kernel via the SVC instruction is documented in [[Kernel_ABI|Kernel ABI]].'''

{| class="wikitable" border="1"
|-
! Id
! NF ARM11
! NF ARM9
! TF ARM11
! Description
! scope="col" width="200" | Notes
|-
| 0x01
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|ControlMemory]](u32* outaddr, u32 addr0, u32 addr1, u32 size, [[Memory Management#enum_MemoryOperation|MemoryOperation]] operation, [[Memory Management#enum_MemoryPermission|MemoryPermission]] permissions)
| Outaddr is usually the same as the input addr0.
|-
| 0x02
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|QueryMemory]]([[Memory Management#struct MemoryInfo|MemoryInfo]]* info, [[Memory Management#struct PageInfo|PageInfo]]* out, u32 Addr)
|
|-
| 0x03
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| void ExitProcess(void)
|
|-
| 0x04
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessAffinityMask(u8* affinitymask, Handle process, s32 processorcount)
|
|-
| 0x05
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetProcessAffinityMask(Handle process, u8* affinitymask, s32 processorcount)
|
|-
| 0x06
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessIdealProcessor(s32 *idealprocessor, Handle process)
|
|-
| 0x07
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetProcessIdealProcessor(Handle process, s32 idealprocessor)
|
|-
| 0x08
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateThread|CreateThread]](Handle* thread, func entrypoint, u32 arg, u32 stacktop, s32 threadpriority, s32 processorid)
|
|-
| 0x09
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| void [[Multi-threading#ExitThread|ExitThread]](void)
|
|-
| 0x0A
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| void [[Multi-threading#SleepThread|SleepThread]](s64 nanoseconds)
|
|-
| 0x0B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#GetThreadPriority|GetThreadPriority]](s32* priority, Handle thread)
|
|-
| 0x0C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#SetThreadPriority|SetThreadPriority]](Handle thread, s32 priority)
|
|-
| 0x0D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetThreadAffinityMask|GetThreadAffinityMask]](u8* affinitymask, Handle thread, s32 processorcount)
|
|-
| 0x0E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#SetThreadAffinityMask|SetThreadAffinityMask]](Handle thread, u8* affinitymask, s32 processorcount)
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].
|-
| 0x0F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetThreadIdealProcessor|GetThreadIdealProcessor]](s32* processorid, Handle thread)
|
|-
| 0x10
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#SetThreadIdealProcessor|SetThreadIdealProcessor]](Handle thread, s32 processorid)
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].
|-
| 0x11
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| s32 GetCurrentProcessorNumber(void)
|
|-
| 0x12
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#Run|Run]](Handle process, StartupInfo* info)
| This starts the main() thread. Buf+0 is main-thread priority, Buf+4 is main-thread stack-size.
|-
| 0x13
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateMutex|CreateMutex]](Handle* mutex, bool initialLocked)
|
|-
| 0x14
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#ReleaseMutex|ReleaseMutex]](Handle mutex)
|
|-
| 0x15
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateSemaphore|CreateSemaphore]](Handle* semaphore, s32 initialCount, s32 maxCount)
|
|-
| 0x16
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#ReleaseSemaphore|ReleaseSemaphore]](s32* count, Handle semaphore, s32 releaseCount)
|
|-
| 0x17
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateEvent|CreateEvent]](Handle* event, ResetType resettype)
|
|-
| 0x18
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#SignalEvent|SignalEvent]](Handle event)
|
|-
| 0x19
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#ClearEvent|ClearEvent]](Handle event)
|
|-
| 0x1A
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result CreateTimer(Handle* timer, ResetType resettype)
|
|-
| 0x1B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result SetTimer(Handle timer, s64 initial_nanoseconds, s64 interval)
|
|-
| 0x1C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result CancelTimer(Handle timer)
|
|-
| 0x1D
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result ClearTimer(Handle timer)
|
|-
| 0x1E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|CreateMemoryBlock]](Handle* memblock, u32 addr, u32 size, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermission, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)
|
|-
| 0x1F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|MapMemoryBlock]](Handle memblock, u32 addr, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermissions, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)
|
|-
| 0x20
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|UnmapMemoryBlock]](Handle memblock, u32 addr)
|
|-
| 0x21
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#Address_Arbiters|CreateAddressArbiter]](Handle* arbiter)
|
|-
| 0x22
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#Address_Arbiters|ArbitrateAddress]](Handle arbiter, u32 addr, ArbitrationType type, s32 value, s64 nanoseconds)
|
|-
| 0x23
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result CloseHandle(Handle handle)
|
|-
| 0x24
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result WaitSynchronization1(Handle handle, s64 timeout_nanoseconds)
|
|-
| 0x25
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result WaitSynchronizationN(s32* out, Handle* handles, s32 handlecount, bool waitAll, s64 timeout_nanoseconds)
|
|-
| 0x26
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SignalAndWait(s32* out, Handle signal, Handle* handles, s32 handleCount, bool waitAll, s64 nanoseconds)
| Stubbed
|-
| 0x27
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result DuplicateHandle(Handle* out, Handle original)
|
|-
| 0x28
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| s64 GetSystemTick(void) (This returns the total CPU ticks elapsed since the CPU was powered-on)
|
|-
| 0x29
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetHandleInfo(s64* out, Handle handle, HandleInfoType type)
|
|-
| 0x2A
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result GetSystemInfo(s64* out, SystemInfoType type, s32 param)
|
|-
| 0x2B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result GetProcessInfo(s64* out, Handle process, ProcessInfoType type)
|
|-
| 0x2C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#GetThreadInfo|GetThreadInfo]](s64* out, Handle thread, ThreadInfoType type)
|
|-
| 0x2D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|ConnectToPort]](Handle* out, const char* portName)
|
|-
| 0x2E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest1(Handle session)
| Stubbed
|
|-
| 0x2F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest2(Handle session)
| Stubbed
|
|-
| 0x30
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest3(Handle session)
| Stubbed
|
|-
| 0x31
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest4(Handle session)
| Stubbed
|
|-
| 0x32
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|SendSyncRequest]](Handle session)
|
|-
| 0x33
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result OpenProcess(Handle* process, u32 processId)
|
|-
| 0x34
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#OpenThread|OpenThread]](Handle* thread, Handle process, u32 threadId)
|
|-
| 0x35
| style="background: green" | Yes
| style="background: red" | No
| style="background: green" | Yes
| Result GetProcessId(u32* processId, Handle process)
|
|-
| 0x36
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetProcessIdOfThread|GetProcessIdOfThread]](u32* processId, Handle thread)
|
|-
| 0x37
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#GetThreadId|GetThreadId]](u32* threadId, Handle thread)
|
|-
| 0x38
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetResourceLimit(Handle* resourceLimit, Handle process)
|
|-
| 0x39
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetResourceLimitLimitValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)
|
|-
| 0x3A
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetResourceLimitCurrentValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)
|
|-
| 0x3B
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetThreadContext|GetThreadContext]](ThreadContext* context, Handle thread)
| Stubbed
|-
| 0x3C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Break(BreakReason reason)
Break(BreakReason debugReason, const void* croInfo, u32 croInfoSize)
|
|-
| 0x3D
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| OutputDebugString(void const, int)
| Does nothing on non-debug units.
|-
| 0x3E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| ControlPerformanceCounter(unsigned long long, int, unsigned int, unsigned long long)
|
|- style="border-top: double"
| 0x47
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|CreatePort]](Handle* portServer, Handle* portClient, const char* name, s16 maxSessions)
| Setting name=NULL creates a private port not accessible from svcConnectToPort.
|-
| 0x48
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|CreateSessionToPort]](Handle* session, Handle port)
|
|-
| 0x49
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|CreateSession]](Handle* sessionServer, Handle* sessionClient)
|
|-
| 0x4A
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|AcceptSession]](Handle* session, Handle port)
|
|-
| 0x4B
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive1(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4C
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive2(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive3(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive4(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC#svcReplyAndReceive|ReplyAndReceive]](s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
|
|-
| 0x50
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[#Interrupt Handling|BindInterrupt]](Interrupt name, Handle eventOrSemaphore, s32 priority, bool isLevelHighActive)
|
|-
| 0x51
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result UnbindInterrupt(Interrupt name, Handle eventOrSemaphore)
|
|-
| 0x52
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result InvalidateProcessDataCache(Handle process, void* addr, u32 size)
|
|-
| 0x53
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result StoreProcessDataCache(Handle process, void const* addr, u32 size)
|
|-
| 0x54
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result FlushProcessDataCache(Handle process, void const* addr, u32 size)
|
|-
| 0x55
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Corelink DMA Engines|StartInterProcessDma]](Handle* dma, Handle dstProcess, void* dst, Handle srcProcess, const void* src, u32 size, const DmaConfig* config)
|
|-
| 0x56
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result StopDma(Handle dma)
|
|-
| 0x57
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result GetDmaState(DmaState* state, Handle dma)
|
|-
| 0x58
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| RestartDma(Handle, void *, void const*, unsigned int, signed char)
|
|-
| 0x59
| style="background: green" | Yes
| style="background: red" | No?
| style="background: red" | No
| SetGpuProt(s8 input_flag). Implemented with [[11.3.0-36|11.3.0-X]], see below.
|-
| 0x5A
| style="background: green" | Yes
| style="background: red" | No?
| style="background: red" | No
| SetWifiEnabled(s0 input_flag). Implemented with [[11.4.0-37|11.4.0-X]], see below.
|- style="border-top: double"
| 0x60
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result DebugActiveProcess(Handle* debug, u32 processID)
|
|-
| 0x61
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result BreakDebugProcess(Handle debug)
|
|-
| 0x62
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result TerminateDebugProcess(Handle debug)
|
|-
| 0x63
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessDebugEvent(DebugEventInfo* info, Handle debug)
|
|-
| 0x64
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ContinueDebugEvent(Handle debug, u32 flags)
|
|-
| 0x65
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessList(s32* processCount, u32* processIds, s32 processIdMaxCount)
|
|-
| 0x66
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetThreadList(s32* threadCount, u32* threadIds, s32 threadIdMaxCount, Handle domain)
|
|-
| 0x67
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetDebugThreadContext(ThreadContext* context, Handle debug, u32 threadId, u32 controlFlags)
|
|-
| 0x68
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetDebugThreadContext(Handle debug, u32 threadId, const ThreadContext* context, u32 controlFlags)
|
|-
| 0x69
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result QueryDebugProcessMemory(MemoryInfo* blockInfo, PageInfo* pageInfo, Handle debug, u32 addr)
|
|-
| 0x6A
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReadProcessMemory(void* buffer, Handle debug, u32 addr, u32 size)
|
|-
| 0x6B
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result WriteProcessMemory(Handle debug, void const* buffer, u32 addr, u32 size)
|
|-
| 0x6C
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetHardwareBreakPoint(s32 registerId, u32 control, u32 value)
|
|-
| 0x6D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| [[Multi-threading#GetDebugThreadParam|GetDebugThreadParam]](s64* unused, u32* out, Handle kdebug, u32 threadId, DebugThreadParameter param)
|
|- style="border-top: double"
| 0x70
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ControlProcessMemory(Handle KProcess, unsigned int Addr0, unsigned int Addr1, unsigned int Size, unsigned int Type, unsigned int Permissions)
|
|-
| 0x71
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management#Memory_Mapping|MapProcessMemory]](Handle process, u32 startAddr, u32 size)
|
|-
| 0x72
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management#Memory_Mapping|UnmapProcessMemory]](Handle process, u32 startAddr, u32 size)
|
|-
| 0x73
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#CreateCodeSet|CreateCodeSet]](Handle* handle_out, struct CodeSetInfo, u32 code_ptr, u32 ro_ptr, u32 data_ptr)
|
|-
| 0x74
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result RandomStub()
| Stubbed
|-
| 0x75
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#CreateProcess|CreateProcess]](Handle* handle_out, Handle codeset_handle, u32 [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|arm11kernelcaps_ptr]], u32 arm11kernelcaps_num)
|
|-
| 0x76
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| TerminateProcess(Handle)
|
|-
| 0x77
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetProcessResourceLimits(Handle KProcess, Handle KResourceLimit)
|
|-
| 0x78
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result CreateResourceLimit(Handle *KResourceLimit)
|
|-
| 0x79
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetResourceLimitValues(Handle res_limit, LimitableResource* resource_type_list, s64* resource_list, u32 count)
|
|-
| 0x7A
| style="background: green" | Yes
| style="background: red" | No
| style="background: green" | Yes
| AddCodeSegment (unsigned int Addr, unsigned int Size)
| Stubbed on NATIVE_FIRM beginning with [[2.0.0-2]]. Used during TWL_FIRM boot.
|-
| 0x7B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: red" | No
| Backdoor(unsigned int CodeAddress)
| This is used on ARM9 NATIVE_FIRM.
No ARM11 processes have access to it without some form of kernelhax, and this was removed on [[11.0.0-33]] (for ARM11).

|-
| 0x7C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| KernelSetState(unsigned int Type, ...)
| The type determines the args to be passed
|-
| 0x7D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result QueryProcessMemory(MemInfo *Info, unsigned int *Out, Handle KProcess, unsigned int Addr)
|
|- style="border-top: double"
| 0xFF
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Stop point
| The svcaccesscontrol mask doesn't apply for this SVC. This svc doesn't check the "debug mode enabled" flag either. Does nothing if there is no [[KDebug]] object associated to the current process. Stubbed on ARM9 NATIVE_FIRM.
|}
NF: NATIVE_FIRM. TF: TWL_FIRM.

Note that "stubbed" here means that the SVC only returns an error, as in the following snippet:

<pre>ROM:FFF04D98 LDR R0, =0xF8C007F4
ROM:FFF04D9C BX LR</pre>

= Types and structures =

== enum ResetType ==

{| class="wikitable" border="1"
! Reset type
! Id
|-
| ONESHOT
| 0
|-
| STICKY
| 1
|-
| PULSE
| 2
|}

Timers/Events may be waited on by a thread using svcWaitSynchronization. Once the timer runs out/the event gets signaled, threads waiting on the respective handles until the timer/event is reset. STICKY timers/events wake up threads until they are explicitly reset by some thread. ONESHOT timers/events will wake up exactly one thread and then are reset automatically. PULSE timers will be reset after waking up one thread too, but will also be started again immediately. It's unknown whether PULSE is a valid reset type for events.

== struct StartupInfo ==
{| class="wikitable" border="1"
! Type
! Field
|-
| s32
| Priority
|-
| u32
| Stack size
|-
| s32
| argc
|-
| s16*
| argv
|-
| s16*
| envp
|}

== enum BreakReason ==
{| class="wikitable" border="1"
! Break Reason
! Value
|-
| PANIC
| 0
|-
| ASSERT
| 1
|-
| USER
| 2
|}

== struct DebugEventInfo ==
Size: 0x28 bytes

When using svcGetProcessDebugEvent, the kernel fetches the first [[KEventInfo]] instance of the process's [[KDebug]]. The debug event is handled and parsed into this structure.

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Event type
|-
| u32
| Thread ID (not used in all events)
|-
| u32
| Flags. Bit0 means that svcContinueDebugEvent needs to be called for this event
|-
| u8[4]
| Remnants of the corresponding flags in [[KEventInfo]], always 0 here
|-
| u32[6]
| Event-specific data (see below)
|}

{| class="wikitable" border="1"
! Event type
! Id
|-
| ATTACH PROCESS
| 0
|-
| ATTACH THREAD
| 1
|-
| EXIT THREAD
| 2
|-
| EXIT PROCESS (1)
| 3
|-
| EXCEPTION
| 4
|-
| DLL LOAD (3)
| 5
|-
| DLL UNLOAD (3)
| 6
|-
| SCHEDULE IN (1) (2)
| 7
|-
| SCHEDULE OUT (1) (2)
| 8
|-
| SYSCALL IN (1) (2)
| 9
|-
| SYSCALL OUT (1) (2)
| 10
|-
| OUTPUT STRING
| 11
|-
| MAP (1) (2)
| 12
|}

<nowiki>(1)</nowiki> Non-blocking: all other events preempt and block all the threads of their process until they are continued.

<nowiki>(2)</nowiki> There is handling code in the kernel but nothing signal those events.

<nowiki>(3)</nowiki> Completely removed from the kernel, but referenced in DMNT. Stubbed relocation code (e.g., in Process9 and in PXI sysmodule) and even whole libraries (e.g., in PXI sysmodule's .rodata section) seem to indicate that Nintendo used dynamic libraries early in system development.

When calling svcDebugActiveProcess, an ATTACH PROCESS debug event is signaled, then ATTACH THREAD for each of its opened threads, then finally ATTACH BREAK.

ATTACH THREAD events are also emitted when a thread is created from an attached process.

=== ATTACH PROCESS event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u64
| Program ID
|-
| char[8]
| Process name
|-
| u32
| Process ID
|-
| u32
| "Other" flag. Always 0 in available kernel versions
|}

=== ATTACH THREAD event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Creator thread ID (0 if attached by svcDebugActiveProcess)
|-
| void *
| Thread local storage
|-
| u32 *
| Entrypoint = .text load address of the parent process
|}

=== EXIT THREAD/PROCESS events ===

A single u32 reason field is used.

Thread exit reasons:
{| class="wikitable" border="1"
! Reason
! Id
|-
| (None)
| 0
|-
| TERMINATE
| 1
|-
| EXIT PROCESS
| 2
|-
| TERMINATE PROCESS
| 3
|}

Process exit reasons:
{| class="wikitable" border="1"
! Reason
! Id
|-
| (None)
| 0
|-
| TERMINATE
| 1
|-
| DEBUG TERMINATE
| 2
|}

=== EXCEPTION event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Exception type
|-
| u32
| Exception address
|-
| u32[4]
| Type-specific data, see below
|}

Exception types:
{| class="wikitable" border="1"
! Exception type
! Id
|-
| UNDEFINED INSTRUCTION
| 0
|-
| PREFETCH ABORT
| 1
|-
| DATA ABORT
| 2
|-
| UNALIGNED DATA ACCESS
| 3
|-
| ATTACH BREAK
| 4
|-
| STOP POINT
| 5
|-
| USER BREAK
| 6
|-
| DEBUGGER BREAK
| 7
|-
| UNDEFINED SYSCALL
| 8
|}

==== UNDEFINED INSTRUCTION/PREFETCH ABORT/DATA ABORT/UNALIGNED DATA ACCESS/UNDEFINED SYSCALL events ====
{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Fault information: Fault Address Register (for DATA ABORT and UNALIGNED DATA ACCESS),
attempted SVC ID (for UNDEFINED SYSCALL), otherwise 0
|}

==== STOP POINT event ====
{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Stop point type that caused the event: 0 = svc 0xFF, 1 = breakpoint, 2 = watchpoint
|-
| u32
| Fault information: FAR for watchpoints, 0 otherwise
|}

==== USER BREAK event ====
{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Break reason
|-
| u32[2]
| Info for LOAD_RO and UNLOAD_RO
|}

User break types:
{| class="wikitable" border="1"
! Reason
! Id
|-
| PANIC
| 0
|-
| ASSERT
| 1
|-
| USER
| 2
|-
| LOAD_RO
| 3
|-
| UNLOAD_RO
| 4
|}

==== DEBUGGER BREAK event ====
{| class="wikitable" border="1"
! Type
! Field
|-
| s32[4]
| IDs of the attached process's threads that were running on each core at the time of the @ref svcBreakDebugProcess call, or -1 (only the first 2 values are meaningful on O3DS).
|}

=== SCHEDULE/SYSCALL IN/OUT events ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u64
| Clock tick
|-
| u32
| CPU ID (SCHEDULE events) Syscall (SYSCALL events)
|}

=== OUTPUT STRING event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| String address
|-
| u32
| String size
|}

=== MAP event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Mapped address
|-
| u32
| Mapped size
|-
| u32
| MemoryPermission
|-
| u32
| MemoryState
|}

== struct ThreadContext ==

Size: 0xCC bytes

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| CpuRegisters
| Saved CPU registers (r0-r12, sp, lr, pc, cpsr)
|-
| 0x44
| FpuRegisters
| Saved FPU registers (d0-d15, fpscr, fpexc)
|}

The user needs to adjust pc for exceptions that occured while in Thumb mode.

'''Flags for svcGetDebugThreadContext/svcSetDebugThreadContext''':

{| class="wikitable" border="1"
|-
! Bit
! Description
|-
| 0
| Get/set CPU GPRs (r0-r12)
|-
| 1
| Get/set CPU SPRs (sp, lr, pc, cpsr)
|-
| 2
| Get/set FPU GPRs (d0-d15 aka. f0-f31)
|-
| 3
| Get/set FPU SPRs (fpscr, fpexc)
|}

When setting CPSR, the following assignment is done: <code>ctx->cpsr = ctx->cpsr & 0x7F0FDFF | userCtx->cpuRegisters.cpsr & 0xF80F0200;</code>. This is to avoid obvious security issues.

== enum DebugThreadParameter ==

{| class="wikitable" border="1"
! Parameter
! Id
|-
| PRIORITY
| 0
|-
| SCHEDULING_MASK_LOW
| 1
|-
| CPU_IDEAL
| 2
|-
| CPU_CREATOR
| 3
|}

== typedef Handle ==

User-visible references to internal objects are represented by 32-bit integers called handles. Handles are only valid in the process they have been created in; hence, they cannot be exchanged between processes directly (the [[IPC]] functions provide a mean to copy handles to other processes, though).

There are a number of special-purpose handles, which provide easy access to information on objects in the current process:
{| class="wikitable" border="1"
! Handle
! Description
|-
| 0xFFFF8000
| Handle to the active thread
|-
| 0xFFFF8001
| Handle to the active process
|}

=svcSetHardwareBreakPoint=
This is essentially an interface for writing values to the debug-unit (B/W)RP registers. registerId range 0..5 = breakpoints(BRP0-5), 0x100..0x101 = watchpoints(WRP0-1), anything outside of these ranges will result in an error. This is used for both adding and removing/disabling breakpoints/watchpoints, hence the raw control value parameter.

Here the kernel sets bit15 in the DSCR, to enable monitor-mode debugging.

Regardless of whether this is for a BRP, when bit21 is set in the control input parameter(BRP type = contextID), the kernel will load the target process [[KProcess|contextID]] and use that internally for the value field. The target process is specified via a [[KDebug]] handle passed as the "value" parameter.

Lastly, the kernel disables the specified (B/W)RP, then writes the value parameter / loaded contextID to the (B/W)VR, then writes the input control value to the (B/W)CR.

= [[DMA]] =
The CTRSDK code for using svcStartInterProcessDma will execute svcBreak when svcStartInterProcessDma returns an error(except for certain error value(s)). Therefore on retail, triggering a svcStartInterProcessDma via a system-module which results in an error from svcStartInterProcessDma will result in the system-module terminating.

= Interrupt Handling =

svcBindInterrupt registers the given event or semaphore corresponding to the handle to the global [[ARM11_Interrupts#Interrupt_Table_.28New3DS.29|"interrupt table"]] for the given interrupt ID. Interrupts 0-14 and 16-31 can never be mapped regardless of the [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|interrupt flags of the process's exheader]], and the latter are not checked when mapping interrupt 15. The "is level high active"/"is manual clear" parameter must be false when binding a semaphore handle (otherwise 0xD8E007EE "invalid combination" is returned).

If something was already registered for the given ID, svcBindInterrupt returns error 0xD8E007F0. See [[KBaseInterruptEvent]] for more information on what happens on receipt of an interrupt.

Applications hence can wait for specific interrupts to happen by calling WaitSynchronization(N) on the event or semaphore handles.

The set of existing ARM11 interrupts is listed on [[ARM11 Interrupts|this page]].

= Debugging =
DebugActiveProcess is used to attach to a process for debugging. This SVC can only be used when the target process' ARM11 descriptors stored in the exheader have the kernel flag for "Enable debug" set. Otherwise when that flag is clear, the kernel flags for the process using this SVC must have the "Force debug" flag set.

This SVC can only be used when a certain kernel state debug flag is non-zero(it's set to zero for retail).

= KernelSetState =
KernelSetState uses the 6th [[ARM11_Interrupts#Private_Interrupts|software-generated interrupt]] for any operation involving synchronization between cores.

{| class="wikitable" border="1"
|-
! Type
! Enabled for the NATIVE_FIRM ARM11 kernel
! Enabled for the TWL_FIRM ARM11 kernel
! Description
|-
| 0
| Yes
| No
| Arguments : <code>u64 firmTitleID</code> (the high 32-bits of that title ID (0 when using N3DS pm) have a special meaning on N3DS, they're otherwise ignored, see below).
This initializes the programID for launching [[FIRM]], then triggers launching [[FIRM]]. With New3DS kernel, it forces the firm title ID to be the New3DS NATIVE_FIRM, when the input firm title ID is 2. The high firm title ID is always set to 0x40138. On New3DS, the kernel disables the additional New3DS cache hw prior to calling the firmlaunch function from the <handler for the KernelSetState-types called via funcptr>.
|-
| 1
| Yes
| Yes
| Does nothing.
|-
| 2
| Yes
| Yes
| Powers down the GPU and syncs with Process9 (waits for <code>*(vu8 *)PXI_SYNC11</code> to be 1) during the process.
On New3DS, the kernel disables the additional New3DS cache hw, when it's actually enabled, prior to executing the rest of the code from the <handler for the KernelSetState-types called via funcptr>.
|-
| 3
| Yes
| No
| Arguments: <code>0, void* address</code> or <code>1</code>
This used for initializing the 0x1000-byte buffer used by the launched [[FIRM]]. When the first parameter is 1, this buffer is copied to the beginning of FCRAM at 0xE0000000. When it is 0, this kernel buffer is mapped to the process address specified by the second argument.
|-
| 4
| No
| Yes
| This unmaps(?) the following virtual memory by writing value physaddr (where physaddr base is 0x80000000) to the L1 MMU table entries: 0x00300000..0x04300000, 0x08000000..0x0FE00000, and 0x10000000..0xF8000000.
|-
| 5
| Yes
| Yes
| Used by kernelpanic. This makes core0 enter a WFI/B infinite loop. Threads that were created on core1 or core2 have their priority set to 0x3F, except if the thread was created on core1 and whose parent process (if any) has the "Runnable on sleep" [[NCCH/Extended_Header#ARM11_Kernel_Flags|ARM11 kernel flag]] set. Core1 threads with a priority of 0x40 without a parent process have their priority set to 0x3E.

Prior to first invoking this handler, the global variable holding <code>UNITINFO != 0</code> is true, and if there is no [[LCD_Registers#Fill_Color|LCD fill]] set at the time kernelpanic is called, kernelpanic fills the top screen with red and the bottom screen with either yellow (if the current process was running under the APPLICATION memregion) or red.

Before invoking this handler a second time, kernelpanic wait for the user to hold L+R+Start+Select down.
|-
| 6
| Yes
| No
| Arguments: <code>u32 what, u64 val</code>
UNITINFO needs to be non-zero.

If <code>what</code> is 0 or any invalid value, nothing is done.

If it is 1, <code>val != 0</code> is written to the global variable enabling ERR:F-format register dumps on user-mode CPU/VFP exceptions (the VFP exception handler acts as if this variable was always true and works on retail environments). The user handler, stack pointer to use for exception handling, and pointer to use for the exception info structure are contiguously located in either the thread's TLS, or if the handler is NULL, in the main thread's TLS, at offset 0x40. If the specified stack pointer is 1, sp_usr - 0x5c is used instead; if the specified exception info buffer is 1, sp_usr - 0x5c is used instead, and if it is 0, <specified stack> - 0x5c is used (0x5c is the size of the exception info structure that is being pushed). Configured by NS on startup on dev-units (default being 0 on non-debugger/jtag units) using the 0x000F0000 configuration block in the [[Config_Savegame|config savegame]].

If 2, kernelpanic will be called when svcBreak is used by a non-attached process. Configured by NS on startup on dev-units (default being 0 on non-debugger/jtag units) using the 0x000F0000 configuration block in the [[Config_Savegame|config savegame]].

If 3, this changes the scheduling/preemption mode (when no threads are being preempted, otherwise returns error 0xC8A01414), see [[KResourceLimit]] for more details.
|-
| 7
| Yes
| No
| This triggers an MCU (hard) reboot. This reboot is triggered via device address 0x4A on the second [[I2C]] bus (the MCU). Register address 0x20 is written to with value 4. This code will not return.
On New3DS, the kernel disables the additional New3DS cache hw prior to calling the reboot function from the <handler for the KernelSetState-types called via funcptr>.
|-
| 8
| Yes
| No
| Alternate FIRM launch code-path, with different [[PXI]] FIFO word constants. Usually not used. PTM-sysmodule can use this but it's unknown what exactly triggers that in PTM-sysmodule.
|-
| 9
| Yes, implemented at some point after system-version v4.5.
| ?
| Argumens: <code>u64 titleID</code>.
When creating a process, if the process has a non-zero TID equal to the parameter above (which is stored in a global variable), then KProcessHwInfo+0x32 ("process is the currently running app") is set to <code>true</code>.
Used by NS conditionally based on the contents of the [[NS CFA]].
|-
| 10
| Yes
| ?
| Arguments: <code>u32 config</code>
ConfigureNew3DSCPU. Only available for the [[New_3DS]] kernel. The actual code for processing this runs under the <handler for the KernelSetState-types called via funcptr>, which runs on all ARM11 cores. Only bit0-1 of the argument are used here. Bit 0 enables higher core clock, and bit 1 enables additional (L2) cache. This configures the hardware [[PDN_Registers|register]] for the flags listed [[NCCH/Extended_Header#Flag1|here]], among other code which uses the MPCore private memory region registers.
|}

= GetSystemInfo =
{| class="wikitable" border="1"
! SystemInfoType value
! s32 param
! Description
|-
| 0
| 0
| This writes the total used memory size in the following memory regions to out: APPLICATION, SYSTEM, and BASE.
|-
| 0
| 1
| This writes the total used memory size in the APPLICATION memory region to out.
|-
| 0
| 2
| This writes the total used memory size in the SYSTEM memory region to out.
|-
| 0
| 3
| This writes the total used memory size in the BASE memory region to out.
|-
| 2
| Unused
| This writes the FCRAM memory [[Memory_Allocation#FCRAM_Region_Data|used by the kernel]] to out.
|-
| 25
| Unused
| This writes the total number of threads which were directly launched by the kernel, to out. No longer exists with some kernel version?
|-
| 26
| Unused
| This writes the total number of processes which were directly launched by the kernel, to out. For the NATIVE_FIRM/SAFE_MODE_FIRM ARM11 kernel, this is normally 5, for processes sm, fs, pm, loader, and pxi.
|}

= GetProcessInfo =
Input:
R0 = unused
R1 = Handle process
R2 = ProcessInfoType type

Output:
R0 = Result
R1 = output value lower word
R2 = output value upper word

{| class="wikitable" border="1"
! ProcessInfoType value
! Available since system version
! Description
|-
| 0
|
| Returns the amount of executable memory allocated to the process + thread context size + page-rounded size of the external handle table
|-
| 1
|
| Returns the amount of <unknown> memory allocated to the process + thread context size + page-rounded size of the external handle table
|-
| 2
|
| Returns the amount of DMA-able (code, data, IO pages, etc.) memory allocated to the process + thread context size + page-rounded size of the external handle table
|-
| 3
|
| Returns the amount of <unknown> memory allocated to the process + thread context size + page-rounded size of the external handle table
|-
| 4
|
| Returns the amount handles in use by the process.
|-
| 5
|
| Returns the highest count of handles that have been open at once by the process
|-
| 6
|
| Returns <code>*(u32*)(KProcess+0x234)</code> which is always 0
|-
| 7
|
| Returns 0
|-
| 8
|
| Returns the maximum number of threads which can be opened by this process (always 0)
|-
| 9-18
| [[8.0.0-18]]
| This only returns error 0xD8E007ED.
|-
| 19
| Stub: [[8.0.0-18]]. Implementation: [[11.3.0-36|11.3.0-X]].
| Originally this only returned 0xD8E007ED. Now with v11.3 this returns the memregion for the process: out low u32 = [[KProcess]] "Kernel flags from the exheader kernel descriptors" & 0xF00. High out u32 = 0.
|-
| 20
| [[8.0.0-18]]
| low u32 = (0x20000000 - <LINEAR virtual-memory base for this process>). That is, the output value is the value which can be added to LINEAR memory vaddrs for converting to physical-memory addrs.
|-
| 21
| [[8.0.0-18]]. N3DS only.
| Returns the maximum amount of VRAM memory allocatable by the process: 0x800000 bytes if the process has already allocated VRAM memory, otherwise 0 (+ error 0xE0E01BF4)
|-
| 22
| [[8.0.0-18]]. N3DS only.
| Returns the address of the first chunk of VRAM allocated by this process
|-
| 23
| [[8.0.0-18]]. N3DS only.
| Returns the amount of VRAM allocated by this process (?)
|}

= GetHandleInfo =

{| class="wikitable" border="1"
! HandleInfoType value
! Description
|-
| 0
| This returns the time in ticks the KProcess referenced by the handle was created. If a KProcess handle was not given, it will write whatever was in r5, r6 when the svc was called.
|-
| 1
| Get internal refcount for kernel object (not counting the one this SVC adds internally to operate), sign-extended to 64 bits.
|-
| 2
| Unimplemented, returns an uninitialized u64 variable (corresponding to r5-r6, which were not altered outside of userland).
|-
| 0x32107
| Returns (u64) 0.
|}

= svc7B Backdoor =
This saves SVC-mode SP+LR on the user-mode stack, then sets the SVC-mode SP to the user-mode SP. This then calls the specified code in SVC-mode. Once the called code returns, this pops the saved SP+LR off the stack for restoring the SVC-mode SP, then returns from the svc7b handler. Note that this svc7b handler does not disable IRQs, if any IRQs/context-switches occur while the SVC-mode SP is set to the user-mode one here, the ARM11-kernel will crash(which hangs the whole ARM11-side system).

= svc 0x59 =
Implemented with [[11.3.0-36|11.3.0-X]]. Used with GSP module starting with that version. This always returns 0.

When input_flag is not 0x1, it will use value 0x0 internally. When a state field already matches input_flag, this will immediately return. Otherwise, after this SVC finishes running, it will write input_flag to this state field. GSP module uses 0x0 for APPLICATION-memregionid and 0x1 for non-APPLICATION-memregionid.

This writes "<nowiki>0x100 | <val></nowiki>" to [[CONFIG11_Registers#CFG11_GPUPROT|pdnregbase+0x140]], where val depends on input_flag and a kernel state field for [[Configuration_Memory|APPMEMTYPE]].

When input_flag is 0x1 val is fixed:
* Old3DS: 0x3
* New3DS: 0x460

Otherwise, val depends on the kernel APPMEMTYPE state field:
{| class="wikitable" border="1"
|-
! FIRM
! [[Memory_layout|APPMEMTYPE]]
! val
|-
| Old3DS
| 2
| 0x3
|-
| Old3DS
| 3
| 0x5
|-
| Old3DS
| 4
| 0x6
|-
| Old3DS
| Non-value-{2/3/4}
| 0x7
|-
| New3DS
| 7
| 0x490
|-
| New3DS
| Non-value-7
| 0x4F0
|}

This same register is also initialized during kernel boot starting with [[3.0.0-5]], with the following values:
* Old3DS: 0x103
* New3DS: 0x550

= svc 0x5A =
Like what NWM did previously, this one does the following:

if (in_flag)
CFG11_WIFICNT |= 1;
else
CFG11_WIFICNT &= ~1;

= Kernel error-codes =
See [[Error codes]].

{| class="wikitable" border="1"
! Error-code value
! Description
|-
| 0x09401BFE
| Timeout occurred with svcWaitSynchronization*, when timeout is not ~0.
|-
| 0xC8601801
| No more unused/free synchronization objects left to use in a given object's linked list. (KEvent, KMutex, KTimer, KSemaphore, KAddressArbiter, KThread)
|-
| 0xC8601802
| No more unused/free KSharedMemory objects left to use in the KSharedMemory linked list - out of blocks
|-
| 0xC8601809
| No more unused/free KSessions left to use in the KSession linked list - out of sessions
|-
| 0xC860180A
| Not enough free memory available for memory allocation.
|-
| 0xC920181A
| The session was closed by the other process..
|-
| 0xD0401834
| Max connections to port have been exceeded
|-
| 0xD8609013
| Unknown, probably reslimit related?
|-
| 0xD88007FA
| Returned if no KObjectName object in the linked list of such objects matches the port name provided to the svc.
|-
| 0xD8E007ED
| This indicates that a value is outside of the enum being used.
|-
| 0xD8E007F1
| This error indicates Misaligned address.
|-
| 0xD8E007F7
| This error indicates that the input handle used with the SVC does not exist in the process handle-table, or that the handle kernel object type does not match the type used by the SVC.
|-
| 0xD9000402
| Invalid memory permissions for input/output buffers, for svcStartInterProcessDma.
|-
| 0xD9001814
| Failed unprivileged load or store - wrong permissions on memory
|-
| 0xD9001BF7
| This error is returned when the kernel retrieves a pointer to a kernel object, but the object type doesn't match the desired one.
|-
| 0xD92007EA
| This error is returned when a process attempts to use svcCreateMemoryBlock when the process memorytype is the application memorytype, and when addr=0.
|-
| 0xE0E01BF5
| This indicates an invalid address was used.
|-
| 0xF8C007F4
| Invalid type/param0-param3 input for svcKernelSetState. This is also returned for those syscalls marked as stubs.
|}

IPC

2017-06-20T04:08:33Z

Yuriks: Add some usage info for svcReplyAndReceive

The 3DS software stack follows a server/client architecture, where common functionality is provided by global server processes through interfaces called ''ports'' and ''services''. Applications can access this functionality by creating ''sessions'' to the provided services. Technically, this is implemented using ''interprocess communication'' (IPC).

== Concepts ==

=== Sessions ===

Sessions are communication channels consisting of a client and server, through which data can be exchanged in the form of a request and response, respectively. Through sessions, the standard [[#Command Structure|IPC command protocol]] is implemented. Clients use their client session handle to send IPC commands to the server using svcSendSyncRequest, while servers use svcReplyAndReceive to reply. Client sessions can't be used with svcReplyAndReceive. In both cases, the kernel takes care of transferring IPC command data from the [[Thread Local Storage]] of the sending thread to the TLS of the receiving thread. Sessions can be created through svcCreateSession, which provides the caller with the client and server handles.

Sessions are used in their raw form to implement [[FS:OpenFile|file handles]]. In this case, fs-module creates a raw session using svcCreateSession, and provides the "fs:USER" client with the resulting client session handle, keeping the server session handle for its own use. These sessions expose their [[Filesystem services#File service|own set of IPC commands]] which act on the file that was opened through fs:USER.

=== Ports ===

Ports are interfaces for managing multiple client sessions to the same high-level server. Ports are created through svcCreatePort, and can be global or private. A global port is created by passing a name for the port to svcCreatePort. Clients can start IPC sessions to global ports by connecting to the port using svcConnectToPort, passing the desired port name. If the port is private, it is not possible to create a session through svcConnectToPort - sessions can only be created if one has a handle to the port itself, obtained from the call to svcCreatePort. When a client wishes to connect to a port (i.e. create a session), the server must accept the new session using svcAcceptSession. The kernel notifies the server whenever a new session is incoming via the server's port handle. The server can wait for this notification through svcWaitSynchronization or svcReplyAndReceive.

The two global ports usually found on retail are "srv:" ([[Services|service manager]]) and "err:f" ([[ErrDisp]]).

=== Services ===

Services are an abstraction of ports that are managed by service manager. Services cannot be connected to through svcConnectToPort, as the underlying port is a private port. The service name is instead entirely handled by service manager, and the kernel is not aware of it. Clients are instead expected to open a session to a service using the "srv:" port command [[SRV:GetServiceHandle|GetServiceHandle]]. The client process must pass an access permission check for each service (by name) that it attempts to request a session with. These permissions are granted in the "service access control" of the title's [[NCCH/Extended Header#ARM11 Local System Capabilities|extended header]]. A service is registered with service manager using the command [[SRV:RegisterService|RegisterService]].

Internally, service manager creates services by creating a private port which it associates with the desired service name. The resulting server port handle is returned in the RegisterService response, for the server's own use (see ports). To create sessions to a service on behalf of a client, service manager uses svcCreateSessionToPort, passing the client port handle it obtained when creating the port, to the kernel. Service manager then returns the resulting session handle to the client in the GetServiceHandle response.

The majority of 3DS inter-process communication is implemented as services.

=== Shared Memory ===

Communication through port/service requests and replies may incur a big bottleneck when exchanging large amounts of data because the kernel needs to transfer the data between the two involved processes. There is hence a complementary feature to share the same physical memory between two processes. For this purpose, one process needs to create a block of shared memory using svcCreateMemoryBlock such that the other process can map it into its own virtual memory address space using svcMapMemoryBlock. The memory block handle for the latter is provided using a regular IPC command.

Many services use shared memory as a secondary command interface (e.g. [[GSP_Shared_Memory|GSP]]), the processing of which is triggered through an IPC request (cf. [[GSPGPU:TriggerCmdReqQueue]]).

== Message Structure ==

IPC requests are written to the [[Thread Local Storage]] at offset 0x80 and submitted using [[SVC|svcSendSyncRequest]]. If the kernel was able to dispatch the request, the server reply will be written to TLS+0x80 before svcSendSyncRequest returns. By convention, the second word of the response data is an error code (or 0 on success). IPC requests and IPC replies follow the same structure.

Every IPC message starts with a u32 header code. Parameters (if any) are written following this header. There are "normal parameters", which are fixed-size words, and there are "translate parameters", which are of flexible size and each of which begins with a header. The entire command has the following structure:
{| class="wikitable" border="1"
|-
! Word
! Size
! Description
|-
| 0
| 1
| Header code
|-
| 1
| x
| Normal parameters
|-
| 1+x
| y
| Translate parameters
|}

The IPC message header has the following structure:
{| class="wikitable" border="1"
|-
! Bits
! Description
|-
| 0-5
| Total size in words of the translate parameters (=y). Note that this is in general different from the number of translate parameters
|-
| 6-11
| Number of normal parameters (=x)
|-
| 12-15
| Unused
|-
| 16-31
| Command ID
|}

When calling svcSendSyncRequest, the command id specifies a function specific to the target service to call. When calling svcReplyAndReceive, the command ID is generally ignored. However if it's 0xffff (and 0 is passed for the reply target handle), the kernel will omit the IPC reply and just wait for incoming IPC requests.

Each translate parameter starts with a translation descriptor:
{| class="wikitable" border="1"
|-
! Bits
! Description
|-
| 1-3
| Translation type
|}

Translate parameters are modified/translated transparently by the kernel. They are used to transfer handles/buffers between the different processes.

The type of parameter is described by the bits 1-3 in the translation descriptor. Parameter types accepted for sending by the kernel are: 0, 1, 2, 5, 6, 7.

For replies, only 0, 1, 5, 6, 7 are allowed. In other words any type 2 fields must be zeroed before calling svcReplyAndReceive on the server-side. For replies, type 0, 1, and 2 are ignored. Types 5, 6, and 7 do something with the mem pointer upon reply. The type 0 descriptor can be used to ignore parameters. The number of parameters covered by a type-0 descriptor is (desc >> 26) + 1.

=== Handle Translation ===

Translation type 0 is used to send handles across processes. The corresponding translation descriptor has the following structure:
{| class="wikitable" border="1"
|-
! Bits
! Description
|-
| 4
| If set, the handles are closed for the caller. Interaction with bit5 unknown.
|-
| 5
| If set, the following handles are replaced by the process ID. Otherwise, translate each handle between client and server.
|-
| 26-31
| Number of handles following this descriptor (minus one).
|}

Usage examples:
{| class="wikitable" border="1"
|-
! scope="col" width="300" | Usual form
! Description
|-
| 0x00000000 <nowiki>|</nowiki> ((num_handles-1)<<26)

<handle 0>

<handle 1>
...
| Copies the given KHandles to the receiving process, i.e. creating new handles in the target process while keeping around the ones of the source process. When a handle value is 0x0, value 0x0 is written to the destination cmdbuf without doing any actual handle-transfer.
|-
| 0x00000010 <nowiki>|</nowiki> ((num_handles-1)<<26)

<handle 0>

<handle 1>
...
| Moves the given KHandles to the receiving process, i.e. creating new handles in the target process and closing the ones of the source process. When a handle value is 0x0, value 0x0 is written to the destination cmdbuf without doing any actual handle-transfer.
|-
| 0x00000020
<placeholder>
| Let kernel set value to calling process ProcessID.
|}

=== Static Buffer Translation ===

Each thread may set up up to 16 static buffer descriptors in their [[Thread Local Storage]] at offset 0x180. These contain information about buffers in the thread's memory space that may be used for information exchange for communication with other processes. In particular, a static buffer descriptor encodes the address and size of a buffer.

Using IPC requests, data can be transferred from any location in the source process to one of the static buffers set up in the target process. This is done using a translation descriptor of type 1, which is followed by a pointer to the source data. The translation descriptor has the following structure:

{| class="wikitable" border="1"
|-
! Bits
! Description
|-
| 1-3
| Translation type (characteristically 1)
|-
| 10-13
| Static buffer index of the receiving process
|-
| 14-31
| Size in bytes of the transferred data. Specifying an amount larger than the target static buffer will result in a kernelpanic.
|}

When encountering such a translation descriptor, the kernel will look up the static buffer address and size corresponding to the given index and (if the buffer can hold the requested amount of data) will copy the data to the specified location.

Note that the translation descriptor and static buffer descriptor share the same layout. However, it is unknown whether the kernel ever reads fields other than the buffer address and size when dealing with static buffer descriptors.

Usage examples:
{| class="wikitable" border="1"
|-
! scope="col" width="300" | Usual form
! Description
|-
| 0x00000002 <nowiki>|</nowiki> (size<<14) <nowiki>|</nowiki> (static_buffer_id<<10)
<ptr>
| The corresponding value contains a ptr to a buffer of said size, that should be copied to an already set-up buffer in destination process at [[Thread Local Storage]] offset 0x180 + static_buffer_id*8. The static_buffer_id is only 4 bits, making it possible for at most up to 16 buffers in total per thread.
|}

=== Buffer Mapping Translation ===

The IPC subsystem can temporarily map a whole buffer of the sender's memory into the receiver's memory space. This is useful for large buffers, for which the overhead of copying static buffer data around would be too expensive.

This kind of translation is enabled by setting bit3 in the translation descriptor. The other two bits of what's documented as the translation type above are used to specify buffer access permissions of the source process.

Buffers will get mapped at virtual address 0x04000000+ in the destination process. When this translation descriptor is submitted to the kernel through svcReplyAndReceive, the given buffer will be unmapped from the sending process(otherwise the buffer will be left mapped after the cmd-reply is finished). Regardless of the descriptor used here, the MMU-table entries for the source-process(from svcSendSyncRequest) buffers are not changed: memory permissions are left at the original while commands are being processed. The memory permissions for buffers at 0x04000000+ is always RW-, regardless of the actual memory permissions for the source-process buffer. Bitmask 0xFFF(low 12-bits) of the start address of each buffer for 0x04000000+ is the same as bitmask 0xFFF from the source-process buffer address.

The buffer address written into the destination cmdbuf by the kernel with svcSendSyncRequest is the allocated 0x04000000+ buffer. When doing the same with svcSendSyncRequest, the buffer address is the same one from the source cmdbuf(0x04000000+).

The first and last pages of the buffer at 0x04000000+ are allocated under the BASE memregion(with data being copied to/from the original source-process buffer as needed), with the rest being mapped to the original buffer physmem. When the source-process buffer is 0x1000-byte aligned, the first page for 0x04000000+ is mapped directly into the original buffer physmem instead of allocating BASE memory(likewise for the last page when the buffer size is 0x1000-byte aligned).

Each buffer at 0x04000000+ has 1 page of unmapped memory before and after the mapped memory, used for separating each buffer. Hence, the first buffer's page at 0x04000000+ is always mapped starting at 0x04001000 not 0x04000000.

{| class="wikitable" border="1"
|-
! Bits
! Description
|-
| 1-2
| Access permission flags for the source process: 1=read-only, 2=write-only, 3=read/write. Specifying 0 will cause a kernel panic.
|-
| 3
| Characteristically 1 for this translation type.
|-
| 4-31
| Size in bytes of the shared memory block.
|}

Usage examples:
{| class="wikitable" border="1"
|-
! scope="col" width="300" | Usual form
! Description
|-
| 0x00000008
| This command will cause a kernel panic.
|-
| <nowiki>0x0000000A | (size<<4)</nowiki>
<ptr>
| The corresponding value contains a ptr to a buffer of said size. The buffer specified by the source process must have read permission(tested on hardware with a read-only buffer). Used for input buffers.
|-
| 0x0000000C <nowiki>|</nowiki> (size<<4)
<ptr>
| The corresponding value contains a ptr to a buffer of said size. The buffer specified by the source process must have write permission. Used for output buffers. In the destination process with the buffer mapped at 0x04000000+, that buffer has same content as the buffer from the source buffer(like descriptor 0x0000000A). When handling command requests this is handled the same way as 0x0000000A, besides the descriptor type written into the dst cmdbuf and memory permissions.
|-
| 0x0000000E <nowiki>|</nowiki> (size<<4)
<ptr>
| The corresponding value contains a ptr to a buffer of said size. The buffer specified by the source process must have read permission during cmd-request handling(write permission is checked during cmd-reply handling for the original buffer). This isn't known to be used by any processes. When handling command requests this is handled the same way as 0x0000000A, and for handling command replies this is handled the same way as 0x0000000C(besides the descriptor type written into the dst cmdbuf for both of these).
|}

=== Usage Examples for other Translation Types ===

{| class="wikitable" border="1"
|-
! Type
! scope="col" width="300" | Usual form
! Description
|-
| 2
| 0x00000004 <nowiki>|</nowiki> (size<<14) <nowiki>|</nowiki> (static_buffer_id<<4)
<ptr>
| This is typically used for RW buffers over PXI, but any process can use this. The address written to the destination cmd-buf is a phys-addr for a table located in the corresponding static buffer of the receiving process (which must be provided by the latter, otherwise the kernel dereferences NULL). Each static buffer needs to be page-aligned and musn't exceed a page's length (kernelpanic otherwise). This table contains the phys-addrs for the actual data, the array entries have the following format: {u32 *datachunk_physaddr, u32 datachunk_bytesize}.
|-
| 3
| 0x00000006 <nowiki>|</nowiki> (size<<14) <nowiki>|</nowiki> (static_buffer_id<<4)
<ptr>
| Same as above except for read-only buffer. Prior(?) to the kernel version which implemented memory-permission checking for PXI buffers, this was unused and hence triggered a kernelpanic.
|}

== SVCs ==

=== svcReplyAndReceive ===

'''Signature:'''
Result ReplyAndReceive(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)

In a single operation, sends a IPC reply and waits for a new request. <code>handles</code> should be a pointer to an array of <code>handleCount</code> handles.<sup>TODO: Are only port/session handles supported?</sup>
<code>replyTarget</code> should contain a handle to the session to send the reply to. (This us usually the session from which we received the previous request.)
If <code>replyTarget</code> is 0, no reply and the call will simply wait for an incoming event.<sup>TODO: It doesn't seem like the 0xFFFF0000 command id mentioned in the above sections is necessary, but needs confirmation.</sup>

Upon returning, <code>index</code> will contain an index into <code>handles</code> specifying which object changed state.
If it's a server port endpoint, it means that there is a new incoming connection on that port which should be accepted using svcAcceptSession.
If it's a server session endpoint it means that we received a request from that session and should process and then reply to it by calling svcReplyAndReceive again with <code>replyTarget</code> set to that session's handle.

An example of a server svcReplyAndReceive loop is:

#define MAX_CLIENTS 4
Handle server_port = ...;
s32 requesting_index;
Handle handles[1 + MAX_CLIENTS] = { server_port };
s32 connected_clients = 0;
Handle reply_target = 0;

while (true) {
Result res = svcReplyAndReceive(&requesting_index, &handles, 1 + connected_clients, reply_target);

if (res == 0xC920181A) {
// Session was closed by remote
// TODO: Handle disconnects
reply_target = 0;
continue;
}

if (requesting_index == 0) {
// New connection in server_port
ASSERT(connected_client < MAX_CLIENTS);
svcAcceptSession(&handles[1 + connected_clients++], server_port);
reply_target = 0;
continue;
}

reply_target = handles[requesting_index];

// Handle command here and write reply to command buffer
}

IPC

2017-06-20T03:45:05Z

Yuriks: Fix heading levels ("Skip Level 1, it is page name level." https://www.mediawiki.org/wiki/Help:Formatting)

SRV:RegisterService

2017-06-05T04:59:03Z

Yuriks: Add details about semantics of call

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x00030100]
|-
| 1-2
| 8-byte UTF-8 service name
|-
| 3
| Name length
|-
| 4
| Maximum sessions
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code
|-
| 1
| Result code
|-
| 3
| Handle to [[KServerPort]] which will receive incoming connections to the service.
|}

This function registers a new service which can be accessed using [[SRV:GetServiceHandle]]. The service manager will create a new client-server port pair, registering the [[KPort|client endpoint]] under the given name, and returning the [[KServerPort|server endpoint]] for the service to listen on for incoming connections.

NCCH/Extended Header

2017-05-06T18:54:52Z

Yuriks: Undo revision 18301 by Neobrain (talk)

This page documents the format of the '''NCCH Extended Header''', or '''exheader''' for short.

The exheader has two sections:

* The actual exheader data, containing System Control Info (SCI) and Access Control Info (ACI);
* A signed copy of NCCH HDR public key, and exheader ACI. This version of the ACI is used as limitation to the actual ACI.

== Main Structure ==
All values are little endian unless otherwise specified.

See also: [https://github.com/profi200/Project_CTR/blob/master/ctrtool/exheader.h]

{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| <code>0x0</code>
| <code>0x200</code>
| SCI
|-
| <code>0x200</code>
| <code>0x200</code>
| ACI
|-
| <code>0x400</code>
| <code>0x100</code>
| <code>AccessDesc</code> signature (RSA-2048-SHA256)
|-
| <code>0x500</code>
| <code>0x100</code>
| NCCH HDR RSA-2048 public key
|-
| <code>0x600</code>
| <code>0x200</code>
| ACI (for limitation of first ACI)
|}

The <code>AccessDesc</code> signature covers the NCCH HDR public key and second ACI. The <code>AccessDesc</code> public key is initialised by the boot ROM.

When loading the exheader, [[FIRM|Process9]] compares the exheader data with the data in the <code>AccessDesc</code> (note that not everything is compared here). When these don't match, an error is returned. The Process9 code handling this validation was updated with [[6.0.0-11|v6.0]]; the only change in this function seems to be the check for the "Ideal processor" field.

== System Control Info ==
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| <code>0x0</code>
| <code>0x8</code>
| Application title (default is "CtrApp")
|-
| <code>0x8</code>
| <code>0x5</code>
| Reserved
|-
| <code>0xD</code>
| <code>0x1</code>
| Flag (bit 0: <code>CompressExefsCode</code>, bit 1: <code>SDApplication</code>)
|-
| <code>0xE</code>
| <code>0x2</code>
| Remaster version
|-
| <code>0x10</code>
| <code>0xC</code>
| Text code set info
|-
| <code>0x1C</code>
| <code>0x4</code>
| Stack size
|-
| <code>0x20</code>
| <code>0xC</code>
| Read-only code set info
|-
| <code>0x2C</code>
| <code>0x4</code>
| Reserved
|-
| <code>0x30</code>
| <code>0xC</code>
| Data code set info
|-
| <code>0x3C</code>
| <code>0x4</code>
| BSS size
|-
| <code>0x40</code>
| <code>0x180</code> (<code>48*8</code>)
| Dependency [[Title list#00040130 - System Modules|module]] (program ID) list
|-
| <code>0x1C0</code>
| <code>0x40</code>
| <code>SystemInfo</code>
|}

Most of these fields are used in [[LOADER:LoadProcess]].

=== Code Set Info ===
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| <code>0x0</code>
| <code>4</code>
| Address
|-
| <code>0x4</code>
| <code>4</code>
| Physical region size (in page-multiples)
|-
| <code>0x8</code>
| <code>4</code>
| Size (in bytes)
|}

=== System Info ===
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| <code>0x0</code>
| <code>0x8</code>
| <code>SaveData</code> Size
|-
| <code>0x8</code>
| <code>0x8</code>
| Jump ID
|-
| <code>0x10</code>
| <code>0x30</code>
| Reserved
|}

== Access Control Info ==
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| <code>0x0</code>
| <code>0x170</code>
| [[#ARM11 Local System Capabilities|ARM11 local system capabilities]]
|-
| <code>0x170</code>
| <code>0x80</code>
| [[#ARM11 Kernel Capabilities|ARM11 kernel capabilities]]
|-
| <code>0x1F0</code>
| <code>0x10</code>
| [[#ARM9 Access Control|ARM9 access control]]
|}

=== ARM11 Local System Capabilities ===
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| <code>0x0</code>
| <code>0x8</code>
| Program ID
|-
| <code>0x8</code>
| <code>0x4</code>
| Core version (The Title ID low of the required [[FIRM]])
|-
| <code>0xC</code>
| <code>0x2</code>
| [[#Flag1|Flag1]] and [[#Flag2|Flag2]] (both implemented starting from [[8.0.0-18]]).
|-
| <code>0xE</code>
| <code>0x1</code>
| [[#Flag0|Flag0]]
|-
| <code>0xF</code>
| <code>0x1</code>
| Priority
|-
| <code>0x10</code>
| <code>0x20</code> (<code>16*2</code>)
| Resource limit descriptors. The first byte here controls the maximum allowed [[PMApp:SetAppResourceLimit|<code>CpuTime</code>]].
|-
| <code>0x30</code>
| <code>0x20</code>
| [[#Storage Info|Storage info]]
|-
| <code>0x50</code>
| <code>0x100</code> (<code>32*8</code>)
| [[#Service Access Control|Service access control]]
|-
| <code>0x150</code>
| <code>0x10</code> (<code>2*8</code>)
| Extended service access control, support for this was implemented with [[9.3.0-21|9.3.0-X]].
|-
| <code>0x160</code>
| <code>0xF</code>
| Reserved
|-
| <code>0x16F</code>
| <code>0x1</code>
| Resource limit category. (0 = <code>APPLICATION</code>, 1 = <code>SYS_APPLET</code>, 2 = <code>LIB_APPLET</code>, 3 = <code>OTHER</code> (sysmodules running under the BASE memregion))
|}

==== Flag0 ====
{| class="wikitable" border="1"
|-
! Bits
! Description
|-
| <code>0-1</code>
| Ideal processor
|-
| <code>2-3</code>
| Affinity mask
|-
| <code>4-7</code>
| Old3DS system mode
|}

===== Old3DS System Mode =====
{| class="wikitable" border="1"
|-
! Value
! Description
|-
| <code>0</code>
| <code>Prod</code> (64MB of usable application memory)
|-
| <code>1</code>
| <code>Undefined</code> (unusable)
|-
| <code>2</code>
| <code>Dev1</code> (96MB of usable application memory)
|-
| <code>3</code>
| <code>Dev2</code> (80MB of usable application memory)
|-
| <code>4</code>
| <code>Dev3</code> (72MB of usable application memory)
|-
| <code>5</code>
| <code>Dev4</code> (32MB of usable application memory)
|-
| <code>6-7</code>
| <code>Undefined</code> Same as <code>Prod</code>?
|}

In the exheader data, the ideal processor field is a bit-index, while in the <code>AccessDesc</code> the ideal processor field is a bitmask. When the bit specified by the exheader field is not set in the <code>AccessDesc</code> field, an error is returned.

<pre>if((1 << exheaderval) & accessdescval == 0) return error</pre>

During a FIRM-launch when a <code>TitleInfo</code> structure was specified, the field at offset [[FIRM#FIRM_Launch_Parameters|0x400]] in the FIRM-launch parameters is set to the SystemMode of the specified title, however in some cases other values are written there. With [[8.0.0-18]] NS will now check the output of [[PTM|PTMSYSM]] command <code>0x040A0000</code>, when the output is non-zero and a certain NS state field is value-zero, the following is executed otherwise this is skipped. With that check passed on [[8.0.0-18]], NS will then check (<code>Flag2 & 0xF</code>). When that is <code>value2</code>, the output value (used for the FIRM-launcher parameter field mentioned above) is set to <code>value7</code>. Otherwise, when that value is non-zero, the output value is set to 6.

==== Flag1 ====
{| class="wikitable" border="1"
|-
! Bits
! Description
|-
| <code>0</code>
| <code>EnableL2Cache</code> (Unknown what this actually does, New3DS-only presumably)
|-
| <code>1</code>
| <code>cpuspeed_804MHz</code> (Default "cpuspeed" when not set)
|-
| <code>2-7</code>
| Unused
|}

In order for the exheader to have any of the above new bits set, the <code>AccessDesc</code> must have the corresponding bit set, otherwise the invalid-exheader error is returned.

Homebrew which runs under a title which has the above <code>cpuspeed</code> flag set, runs much faster on New3DS. It's unknown how exactly the system handles these flags.

When launching titles / perhaps other things with [[APT]], [[NS]] uses [[PTMSYSM:ConfigureNew3DSCPU]] with data which originally came from these flags; NS does this regardless of what the running 3DS system is. However, due to a bug(?) in NS the value sent to that command is always either 0x0 or 0x3. When calculating that value, the code only ever uses the cpuspeed field, not the cache field: code to actually load and check the value of the cache field appears to be missing.

==== Flag2 ====
{| class="wikitable" border="1"
|-
! Bit
! Description
|-
| <code>0-3</code>
| New3DS system mode
|-
| <code>4-7</code>
| Unused
|}

===== New3DS System Mode =====
{| class="wikitable" border="1"
|-
! Value
! Description
|-
| <code>0</code>
| <code>Legacy</code> (use Old3DS system mode)
|-
| <code>1</code>
| <code>Prod</code> (124MB of usable application memory)
|-
| <code>2</code>
| <code>Dev1</code> (178MB of usable application memory)
|-
| <code>3</code>
| <code>Dev2</code> (124MB of usable application memory)
|-
| <code>4-7</code>
| <code>Undefined</code> Same as <code>Prod</code>?
|}

When in <code>Legacy</code> mode, the actual memory layout is the same as in <code>New3DS Prod</code>, except the available application memory as reported to the application is reduced to the Old3DS size.

The exheader value for the New3DS system mode value must be ≤ to the <code>AccessDesc</code> value, otherwise the invalid-exheader error is returned.

==== Storage Info ====
Used in [[FSReg:Register]].

{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| <code>0x0</code>
| <code>8</code>
| Extdata ID
|-
| <code>0x8</code>
| <code>8</code>
| System savedata IDs
|-
| <code>0x10</code>
| <code>8</code>
| Storage accessible unique IDs
|-
| <code>0x18</code>
| <code>7</code>
| Filesystem access info
|-
| <code>0x1F</code>
| <code>1</code>
| Other attributes
|}

File System Access Info:
{| class="wikitable" border="1"
|-
! Bit and bitmask
! Description
|-
| <code>0</code>, <code>0x1</code>
| Category system application
|-
| <code>1</code>, <code>0x2</code>
| Category hardware check
|-
| <code>2</code>, <code>0x4</code>
| Category filesystem tool
|-
| <code>3</code>, <code>0x8</code>
| Debug
|-
| <code>4</code>, <code>0x10</code>
| TWL card backup
|-
| <code>5</code>, <code>0x20</code>
| TWL NAND data
|-
| <code>6</code>, <code>0x40</code>
| BOSS
|-
| <code>7</code>, <code>0x80</code>
| [[FS:OpenArchive|<code>sdmc:/</code>]]
|-
| <code>8</code>, <code>0x100</code>
| Core
|-
| <code>9</code>, <code>0x200</code>
| [[Flash Filesystem|<code>nand:/ro/</code>]] (Read Only)
|-
| <code>10</code>, <code>0x400</code>
| [[Flash Filesystem|<code>nand:/rw/</code>]]
|-
| <code>11</code>, <code>0x800</code>
| [[Flash Filesystem|<code>nand:/ro/</code>]] (Write Access)
|-
| <code>12</code>, <code>0x1000</code>
| Category system settings
|-
| <code>13</code>, <code>0x2000</code>
| Cardboard
|-
| <code>14</code>, <code>0x4000</code>
| Export/Import IVS
|-
| <code>15</code>, <code>0x8000</code>
| [[FS:OpenArchive|<code>sdmc:/</code>]] (Write-only)
|-
| <code>16</code>, <code>0x10000</code>
| Switch cleanup (Introduced in [[3.0.0-5|3.0.0]]?)
|-
| <code>17</code>, <code>0x20000</code>
| Savedata move (Introduced in [[5.0.0-11|5.0.0]])
|-
| <code>18</code>, <code>0x40000</code>
| Shop (Introduced in [[5.0.0-11|5.0.0]])
|-
| <code>19</code>, <code>0x80000</code>
| Shell (Introduced in [[5.0.0-11|5.0.0]])
|-
| <code>20</code>, <code>0x100000</code>
| Category home menu (Introduced in [[6.0.0-11|6.0.0]])
|-
| <code>21</code>, <code>0x200000</code>
| Seed DB. Introduced in [[9.6.0-24|9.6.0-X]] [[FIRM]]. [[Home Menu]] has this bit set starting with [[9.6.0-24|9.6.0-X]].
|}

====Other Attributes====

{| class="wikitable" border="1"
|-
! Bit
! Description
|-
| <code>0</code>
| Not use ROMFS
|-
| <code>1</code>
| Use Extended savedata access.
|}

When Bit1 is set, the "Extdata ID" and "Storage Accessable Unique IDs" regions are used to store a total of 6 "Accessible Save IDs". Introduced in [[6.0.0-11|6.0.0]].

==== Service Access Control ====
This is the list of [[Services_API|services]] which the process is allowed to access, this is registered with the [[Services|services]] manager. Each service listed in the exheader must be listed in the <code>AccessDesc</code>, otherwise the invalid exheader error is returned. The order of the services for exheader/<code>AccessDesc</code> doesn't matter. The <code>AccessDesc</code> can list services which are not in the exheader, but normally the service-access-control data for exheader/<code>AccessDesc</code> are exactly the same.

This list is submitted to [[SRVPM:RegisterProcess]].

=== ARM11 Kernel Capabilities ===
The kernel capability descriptors are passed to [[SVC|svcCreateProcess]].

{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| <code>0x0</code>
| <code>0x70</code> (<code>28*4</code>)
| Descriptors
|-
| <code>0x70</code>
| <code>0x10</code>
| Reserved
|}

There are different descriptor types, determined by the number of leading ones in the binary value representation of bits 20-31. The different types are laid out as follows:

{| class="wikitable" border="1"
|-
! Pattern of bits 20-31
! Type
! Fields
|-
| <code>0b1110xxxxxxxx</code>
| Interrupt info
|
|-
| <code>0b11110xxxxxxx</code>
| System call mask
| Bits 24-26: System call mask table index; Bits 0-23: mask
|-
| <code>0b1111110xxxxx</code>
| Kernel release version
| Bits 8-15: Major version; Bits 0-7: Minor version
|-
| <code>0b11111110xxxx</code>
| Handle table size
| Bits 0-18: size
|-
| <code>0b111111110xxx</code>
| [[#ARM11_Kernel_Flags|Kernel flags]]
| See below
|-
| <code>0b11111111100x</code>
| Map address range
| Describes a memory mapping like the 0b111111111110 descriptor, but an entire range rather than a single page is mapped. Another 0b11111111100x descriptor must follow this one to denote the (exclusive) end of the address range to map.
|-
| <code>0b111111111110</code>
| Map memory page
| Bits 0-19: page index to map (virtual address >> 12; the physical address is determined per-page according to [[Memory layout]]); Bit 20: Map read-only (otherwise read-write)
|}

==== ARM11 Kernel Flags ====
{| class="wikitable" border="1"
|-
! Bit
! Description
|-
| <code>0</code>
| Allow debug
|-
| <code>1</code>
| Force debug
|-
| <code>2</code>
| Allow non-alphanum
|-
| <code>3</code>
| Shared page writing
|-
| <code>4</code>
| Privilege priority
|-
| <code>5</code>
| Allow <code>main()</code> args
|-
| <code>6</code>
| Shared device memory
|-
| <code>7</code>
| Runnable on sleep
|-
| <code>8-11</code>
| Memory type (1: application, 2: system, 3: base)
|-
| <code>12</code>
| [[Memory_layout#NATIVE_FIRM.2FSAFE_MODE_FIRM_Userland_Memory|Special memory]]
|-
| <code>13</code>
| Process has access to CPU core 2 (New3DS only)
|}

=== ARM9 Access Control ===
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| <code>0x0</code>
| <code>15</code>
| Descriptors
|-
| <code>0xF</code>
| <code>1</code>
| ARM9 Descriptor Version. Originally this value had to be ≥ 2. Starting with [[9.3.0-21|9.3.0-X]] this value has to be either value 2 or value 3.
|}

Descriptors:
{| class="wikitable" border="1"
|-
! Bit
! Description
|-
| <code>0</code>
| Mount [[Flash Filesystem|<code>nand:/</code>]]
|-
| <code>1</code>
| Mount [[Flash Filesystem|<code>nand:/ro/</code>]] (Write Access)
|-
| <code>2</code>
| Mount [[Flash Filesystem|<code>twln:/</code>]]
|-
| <code>3</code>
| Mount [[Flash Filesystem|<code>wnand:/</code>]]
|-
| <code>4</code>
| Mount card SPI
|-
| <code>5</code>
| Use SDIF3
|-
| <code>6</code>
| Create seed
|-
| <code>7</code>
| Use card SPI
|-
| <code>8</code>
| SD application (Not checked)
|-
| <code>9</code>
| Mount [[SD Filesystem|sdmc:/]] (Write Access)
|}

GPU/Programming Guide

2016-12-19T05:01:36Z

Yuriks: Correct register used for immediate-mode parameter count

This page is intended to contain more higher-level explanation of concepts and features provided by the 3DS GPU. For more detailed register-level information check [[GPU/Internal Registers]].

= Geometry Pipeline =

== Fixed Vertex Attributes ==

If a certain vertex attribute is constant for the duration of a draw call, instead of specifying a vertex array with repeated contents or changing the shader to use a uniform, ''fixed vertex attributes'' can be used. They let you specify a fixed value, which will be assumed by the attribute for all vertices of the batch.

To use a fixed attribute, set the bit corresponding to the attribute in [[GPU/Internal Registers#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]] and ensure that no vertex arrays are configured for the attribute. (Any configured arrays will override the fixed value, regardless of the bit setting.) Even if a vertex array isn't being used for the attribute it still needs to be counted in the number of active attributes specified in the same register.

To specify the actual value of the fixed attribute, write the attribute index to [[GPU/Internal Registers#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]] followed by writes with packed a float24 4-tuple to the 3 [[GPU/Internal Registers#GPUREG_FIXEDATTRIB_DATA0|GPUREG_FIXEDATTRIB_DATA]] registers. The value is always specified as a float 4-component vector, the configured type is ignored.

== Immediate-Mode Vertex Submission ==

Instead of using vertex arrays to supply vertex data, drawing can be done by directly writing vertex data to a register. This allows vertex data to be inlined directly in the command buffer. Since this is restricted to 4-component float data, it is more useful for small draws like UI elements or debug displays, to avoid using an unreasonable amount of memory and processing time appending the vertices to the command buffer.

To use this feature, configure the number of attributes per vertex in [[GPU/Internal Registers#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]. (All settings in the registers related to the vertex loader are ignored.) Then setup the GPU and shaders the same as if doing a regular draw call with GPUREG_DRAWARRAYS or GPUREG_DRAWELEMENTS, but instead of writing to either register, write the value 0xF to [[GPU/Internal Registers#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]] and then follow by repeatedly writing vertex data to [[GPU/Internal Registers#GPUREG_FIXEDATTRIB_DATA0|GPUREG_FIXEDATTRIB_DATA]].

Each set of writes to the 3 data registers specifies one attribute and all attributes (as configured in GPUREG_VSH_NUM_ATTR) need to be written, in order, to specify a vertex. Drawing happens automatically as vertices are specified. After finishing specifying vertices, follow with the same writes used after a draw arrays/elements.

When drawing using triangle strips or fans, [[GPU/Internal Registers#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]] should be used to end the previous strip before (or while) drawing.

== Drawing elements ==

The 3DS GPU is capable of drawing vertex + index arrays, triggered by [[GPU/Internal_Registers#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]. A set of commands commonly used by the standard GL implementation to accomplish this is as follows:

{| class="wikitable" border="1"
! Command Index
! Register
! Description
|-
| 0
| [[GPU/Internal_Registers#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| Set whether drawing triangle elements
|-
| 1-2
| [[GPU/Internal_Registers#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
| Set whether drawing triangle elements
|-
| 3
| [[GPU/Internal_Registers#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| Set primitive mode
|-
| 4
| [[GPU/Internal_Registers#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| Set number of output map registers
|-
| 5
| [[GPU/Internal_Registers#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
| Trigger reset
|-
| 6
| [[GPU/Internal_Registers#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
| Set function indicator to 0
|-
| 7
| [[GPU/Internal_Registers#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
| Set offset and type
|-
| 8
| [[GPU/Internal_Registers#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
| Set vertex count
|-
| 9
| [[GPU/Internal_Registers#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
| Set mode to drawing
|-
| 10
| [[GPU/Internal_Registers#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
| Trigger draw
|-
| 11
| [[GPU/Internal_Registers#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
| Set mode to configuration
|-
| 12
| [[GPU/Internal_Registers#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
| Trigger post-vertex cache clear
|-
| 13
| [[GPU/Internal_Registers#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
| Flush framebuffer
|-
| 14
| [[GPU/Internal_Registers#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| Clear drawing triangle elements
|-
| 15
| [[GPU/Internal_Registers#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
| Clear drawing triangle elements
|-
| 16
| [[GPU/Internal_Registers#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| Clear primitive mode
|-
| 17
| [[GPU/Internal_Registers#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
| Clear entry point
|}

[[Category:GPU]]

KScheduler

2016-12-04T01:43:48Z

Yuriks:

[[Category:Kernel objects]]

class [[KScheduler]] extends [[KSchedulableInterruptEvent]];

Size : 0x228 bytes

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| void **
| Pointer to vtable
|-
| 0x4
| [[KSynchronizationObject]] *
| Inherited field. Unused.
|-
| 0x8
| u32
| Count for thread switch attempts - this is only added to if a context switch function runs but exits because the scheduler is locked by another thread.
|-
| 0xC
| bool
| Context switch needed
|-
| 0xD
| bool
| Context switch started during interrupt
|-
| 0xE
| bool
| Trigger CPU cross-core interrupt (interrupt 8)
|-
| 0xF
| bool
| Post-interrupt rescheduling needed
|-
| 0x10
| s16
| Scheduler core number
|-
| 0x12
| s16
| Count of threads currently being managed by this scheduler object
|-
| 0x14
| u32
| Bit field for high priority threads in KScheduler(0-31)
|-
| 0x18
| u32
| Bit field for low priority threads in KScheduler(32-63)
|-
| 0x1C
| KThread*
| Scheduler's idle thread (runs when no other runnable thread is available)
|-
| 0x20
| u32
| Unknown
|-
| 0x24
| u32
| Unknown/unused
|-
| 0x28
| ThreadSchedulePrioList[64]
| List of KThread pair structs by priority
|}

ThreadSchedulePrioList struct:
{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| KThread*
| First
|-
| 0x4
| KThread*
| Last
|}

There is 1 KScheduler object per core.

KScheduler instances are mapped to SGI #8. The interrupt handler/callback returns 1, which triggers a post-interrupt rescheduling and context switch (like all the other handlers not returning NULL), but does nothing else in particular.
The second virtual method is stubbed.

ThreadSchedulePrioList info:

Each priority of KThread has a pair of KThread object pointers below the KScheduler object. Each pair of pointers makes up 1 entry in that core's Scheduler for their priority. The first KThread in the entry is the first KThread in the linked list and the second is the last KThread in the linked list of KThreads in the scheduler that have the same priority.

Priority bit fields:

Each bit field goes from the most significant bit to the least significant bit, high priority to low priority. This means, for example, that bit 31 in the high priority bit field is for priority 0 and bit 0 is for priority 31. These fields are set when a KThread with the corresponding priority is added for scheduling and are cleared when the last KThread in the linked list for a given priority is removed from the scheduler.

SVC

2016-08-06T11:05:33Z

Yuriks: /* System calls */

= System calls =
'''Note: The argument-lists here apply to the official syscall wrapper-functions that are found in userland processes. The actual ordering passed to the kernel via the SVC instruction is documented in [[Kernel_ABI|Kernel ABI]].'''

{| class="wikitable" border="1"
|-
! Id
! NF ARM11
! NF ARM9
! TF ARM11
! Description
! scope="col" width="200" | Notes
|-
| 0x01
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|ControlMemory]](u32* outaddr, u32 addr0, u32 addr1, u32 size, [[Memory Management#enum_MemoryOperation|MemoryOperation]] operation, [[Memory Management#enum_MemoryPermission|MemoryPermission]] permissions)
| Outaddr is usually the same as the input addr0.
|-
| 0x02
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|QueryMemory]]([[Memory Management#struct MemoryInfo|MemoryInfo]]* info, [[Memory Management#struct PageInfo|PageInfo]]* out, u32 Addr)
|
|-
| 0x03
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| void ExitProcess(void)
|
|-
| 0x04
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessAffinityMask(u8* affinitymask, Handle process, s32 processorcount)
|
|-
| 0x05
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetProcessAffinityMask(Handle process, u8* affinitymask, s32 processorcount)
|
|-
| 0x06
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessIdealProcessor(s32 *idealprocessor, Handle process)
|
|-
| 0x07
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetProcessIdealProcessor(Handle process, s32 idealprocessor)
|
|-
| 0x08
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateThread|CreateThread]](Handle* thread, func entrypoint, u32 arg, u32 stacktop, s32 threadpriority, s32 processorid)
|
|-
| 0x09
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| void [[Multi-threading#ExitThread|ExitThread]](void)
|
|-
| 0x0A
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| void [[Multi-threading#SleepThread|SleepThread]](s64 nanoseconds)
|
|-
| 0x0B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#GetThreadPriority|GetThreadPriority]](s32* priority, Handle thread)
|
|-
| 0x0C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#SetThreadPriority|SetThreadPriority]](Handle thread, s32 priority)
|
|-
| 0x0D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetThreadAffinityMask|GetThreadAffinityMask]](u8* affinitymask, Handle thread, s32 processorcount)
|
|-
| 0x0E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#SetThreadAffinityMask|SetThreadAffinityMask]](Handle thread, u8* affinitymask, s32 processorcount)
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].
|-
| 0x0F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetThreadIdealProcessor|GetThreadIdealProcessor]](s32* processorid, Handle thread)
|
|-
| 0x10
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#SetThreadIdealProcessor|SetThreadIdealProcessor]](Handle thread, s32 processorid)
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].
|-
| 0x11
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| s32 GetCurrentProcessorNumber(void)
|
|-
| 0x12
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#Run|Run]](Handle process, StartupInfo* info)
| This starts the main() thread. Buf+0 is main-thread priority, Buf+4 is main-thread stack-size.
|-
| 0x13
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateMutex|CreateMutex]](Handle* mutex, bool initialLocked)
|
|-
| 0x14
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#ReleaseMutex|ReleaseMutex]](Handle mutex)
|
|-
| 0x15
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateSemaphore|CreateSemaphore]](Handle* semaphore, s32 initialCount, s32 maxCount)
|
|-
| 0x16
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#ReleaseSemaphore|ReleaseSemaphore]](s32* count, Handle semaphore, s32 releaseCount)
|
|-
| 0x17
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateEvent|CreateEvent]](Handle* event, ResetType resettype)
|
|-
| 0x18
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#SignalEvent|SignalEvent]](Handle event)
|
|-
| 0x19
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#ClearEvent|ClearEvent]](Handle event)
|
|-
| 0x1A
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result CreateTimer(Handle* timer, ResetType resettype)
|
|-
| 0x1B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result SetTimer(Handle timer, s64 initial_nanoseconds, s64 interval)
|
|-
| 0x1C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result CancelTimer(Handle timer)
|
|-
| 0x1D
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result ClearTimer(Handle timer)
|
|-
| 0x1E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|CreateMemoryBlock]](Handle* memblock, u32 addr, u32 size, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermission, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)
|
|-
| 0x1F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|MapMemoryBlock]](Handle memblock, u32 addr, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermissions, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)
|
|-
| 0x20
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|UnmapMemoryBlock]](Handle memblock, u32 addr)
|
|-
| 0x21
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#Address_Arbiters|CreateAddressArbiter]](Handle* arbiter)
|
|-
| 0x22
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#Address_Arbiters|ArbitrateAddress]](Handle arbiter, u32 addr, ArbitrationType type, s32 value, s64 nanoseconds)
|
|-
| 0x23
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result CloseHandle(Handle handle)
|
|-
| 0x24
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result WaitSynchronization1(Handle handle, s64 timeout_nanoseconds)
|
|-
| 0x25
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result WaitSynchronizationN(s32* out, Handle* handles, s32 handlecount, bool waitAll, s64 timeout_nanoseconds)
|
|-
| 0x26
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SignalAndWait(s32* out, Handle signal, Handle* handles, s32 handleCount, bool waitAll, s64 nanoseconds)
| Stubbed
|-
| 0x27
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result DuplicateHandle(Handle* out, Handle original)
|
|-
| 0x28
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| s64 GetSystemTick(void) (This returns the total CPU ticks elapsed since the CPU was powered-on)
|
|-
| 0x29
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetHandleInfo(s64* out, Handle handle, HandleInfoType type)
|
|-
| 0x2A
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result GetSystemInfo(s64* out, SystemInfoType type, s32 param)
|
|-
| 0x2B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result GetProcessInfo(s64* out, Handle process, ProcessInfoType type)
|
|-
| 0x2C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#GetThreadInfo|GetThreadInfo]](s64* out, Handle thread, ThreadInfoType type)
|
|-
| 0x2D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ConnectToPort(Handle* out, const char* portName)
|
|-
| 0x2E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest1(Handle session)
| Stubbed
|
|-
| 0x2F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest2(Handle session)
| Stubbed
|
|-
| 0x30
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest3(Handle session)
| Stubbed
|
|-
| 0x31
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest4(Handle session)
| Stubbed
|
|-
| 0x32
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest(Handle session)
|
|-
| 0x33
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result OpenProcess(Handle* process, u32 processId)
|
|-
| 0x34
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#OpenThread|OpenThread]](Handle* thread, Handle process, u32 threadId)
|
|-
| 0x35
| style="background: green" | Yes
| style="background: red" | No
| style="background: green" | Yes
| Result GetProcessId(u32* processId, Handle process)
|
|-
| 0x36
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetProcessIdOfThread|GetProcessIdOfThread]](u32* processId, Handle thread)
|
|-
| 0x37
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#GetThreadId|GetThreadId]](u32* threadId, Handle thread)
|
|-
| 0x38
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetResourceLimit(Handle* resourceLimit, Handle process)
|
|-
| 0x39
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetResourceLimitLimitValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)
|
|-
| 0x3A
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetResourceLimitCurrentValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)
|
|-
| 0x3B
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetThreadContext|GetThreadContext]](ThreadContext* context, Handle thread)
| Stubbed
|-
| 0x3C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Break(BreakReason)
|
|-
| 0x3D
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| OutputDebugString(void const, int)
| Does nothing on non-debug units.
|-
| 0x3E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| ControlPerformanceCounter(unsigned long long, int, unsigned int, unsigned long long)
|
|- style="border-top: double"
| 0x47
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result CreatePort(Handle* portServer, Handle* portClient, const char* name, s32 maxSessions)
| Setting name=NULL creates a private port not accessible from svcConnectToPort.
|-
| 0x48
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result CreateSessionToPort(Handle* session, Handle port)
|
|-
| 0x49
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result CreateSession(Handle* sessionServer, Handle* sessionClient)
|
|-
| 0x4A
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result AcceptSession(Handle* session, Handle port)
|
|-
| 0x4B
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive1(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4C
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive2(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive3(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive4(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
|
|-
| 0x50
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[#Interrupt Handling|BindInterrupt]](Interrupt name, Handle syncObject, s32 priority, bool isManualClear)
|
|-
| 0x51
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result UnbindInterrupt(Interrupt name, Handle syncObject)
|
|-
| 0x52
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result InvalidateProcessDataCache(Handle process, void* addr, u32 size)
|
|-
| 0x53
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result StoreProcessDataCache(Handle process, void const* addr, u32 size)
|
|-
| 0x54
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result FlushProcessDataCache(Handle process, void const* addr, u32 size)
|
|-
| 0x55
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Corelink DMA Engines|StartInterProcessDma]](Handle* dma, Handle dstProcess, void* dst, Handle srcProcess, const void* src, u32 size, const DmaConfig* config)
|
|-
| 0x56
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result StopDma(Handle dma)
|
|-
| 0x57
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result GetDmaState(DmaState* state, Handle dma)
|
|-
| 0x58
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| RestartDma(nn::Handle, void *, void const*, unsigned int, signed char)
|
|- style="border-top: double"
| 0x60
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result DebugActiveProcess(Handle* debug, u32 processID)
|
|-
| 0x61
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result BreakDebugProcess(Handle debug)
|
|-
| 0x62
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result TerminateDebugProcess(Handle debug)
|
|-
| 0x63
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessDebugEvent(DebugEventInfo* info, Handle debug)
|
|-
| 0x64
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ContinueDebugEvent(Handle debug, u32 flags)
|
|-
| 0x65
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessList(s32* processCount, u32* processIds, s32 processIdMaxCount)
|
|-
| 0x66
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetThreadList(s32* threadCount, u32* threadIds, s32 threadIdMaxCount, Handle domain)
|
|-
| 0x67
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetDebugThreadContext(ThreadContext* context, Handle debug, u32 threadId, u32 controlFlags)
|
|-
| 0x68
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetDebugThreadContext(Handle debug, u32 threadId, ThreadContext* context, u32 controlFlags)
|
|-
| 0x69
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result QueryDebugProcessMemory(MemoryInfo* blockInfo, PageInfo* pageInfo, Handle process, u32 addr)
|
|-
| 0x6A
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReadProcessMemory(void* buffer, Handle debug, u32 addr, u32 size)
|
|-
| 0x6B
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result WriteProcessMemory(Handle debug, void const* buffer, u32 addr, u32 size)
|
|-
| 0x6C
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetHardwareBreakPoint(s32 registerId, u32 control, u32 value)
|
|-
| 0x6D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| [[Multi-threading#GetDebugThreadParam|GetDebugThreadParam]](long long *, int *, nn::Handle, unsigned int, nn::dmnt::DebugThreadParam)
| Disabled on regular kernel.
|- style="border-top: double"
| 0x70
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ControlProcessMemory(Handle KProcess, unsigned int Addr0, unsigned int Addr1, unsigned int Size, unsigned int Type, unsigned int Permissions)
|
|-
| 0x71
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management#Memory_Mapping|MapProcessMemory]](Handle KProcess, unsigned int StartAddr, unsigned int EndAddr)
|
|-
| 0x72
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management#Memory_Mapping|UnmapProcessMemory]](Handle KProcess, unsigned int StartAddr, unsigned int EndAddr)
|
|-
| 0x73
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#CreateCodeSet|CreateCodeSet]](Handle* handle_out, struct CodeSetInfo, u32 code_ptr, u32 ro_ptr, u32 data_ptr)
|
|-
| 0x74
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result RandomStub()
| Stubbed
|-
| 0x75
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#CreateProcess|CreateProcess]](Handle* handle_out, Handle codeset_handle, u32 [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|arm11kernelcaps_ptr]], u32 arm11kernelcaps_num)
|
|-
| 0x76
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| TerminateProcess(Handle)
|
|-
| 0x77
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetProcessResourceLimits(Handle KProcess, Handle KResourceLimit)
|
|-
| 0x78
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result CreateResourceLimit(Handle *KResourceLimit)
|
|-
| 0x79
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetResourceLimitValues(Handle res_limit, LimitableResource* resource_type_list, s64* resource_list, u32 count)
|
|-
| 0x7A
| style="background: green" | Yes
| style="background: red" | No
| style="background: green" | Yes
| AddCodeSegment (unsigned int Addr, unsigned int Size)
| Stubbed on NATIVE_FIRM beginning with [[2.0.0-2]]. Used during TWL_FIRM boot.
|-
| 0x7B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: red" | No
| Backdoor(unsigned int CodeAddress)
| This is used on ARM9 NATIVE_FIRM.
No ARM11 processes have access to it without some form of kernelhax, and this was removed on [[11.0.0-33]] (for ARM11).

|-
| 0x7C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| KernelSetState(unsigned int Type, unsigned int Param0, unsigned int Param1, unsigned int Param2)
| The type determines the meaning of each param
|-
| 0x7D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result QueryProcessMemory(MemInfo *Info, unsigned int *Out, Handle KProcess, unsigned int Addr)
|
|- style="border-top: double"
| 0xFF
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| ???
| Debug related? The svcaccesscontrol mask doesn't apply for this SVC. Stubbed on ARM9 NATIVE_FIRM.
|}
NF: NATIVE_FIRM. TF: TWL_FIRM.

Note that "stubbed" here means that the SVC only returns an error, as in the following snippet:

<pre>ROM:FFF04D98 LDR R0, =0xF8C007F4
ROM:FFF04D9C BX LR</pre>

= Types and structures =

== enum ResetType ==

{| class="wikitable" border="1"
! Reset type
! Id
|-
| ONESHOT
| 0
|-
| STICKY
| 1
|-
| PULSE
| 2
|}

Timers/Events may be waited on by a thread using svcWaitSynchronization. Once the timer runs out/the event gets signaled, threads waiting on the respective handles until the timer/event is reset. STICKY timers/events wake up threads until they are explicitly reset by some thread. ONESHOT timers/events will wake up exactly one thread and then are reset automatically. PULSE timers will be reset after waking up one thread too, but will also be started again immediately. It's unknown whether PULSE is a valid reset type for events.

== struct StartupInfo ==
{| class="wikitable" border="1"
! Type
! Field
|-
| s32
| Priority
|-
| u32
| Stack size
|-
| s32
| argc
|-
| s16*
| argv
|-
| s16*
| envp
|}

== enum BreakReason ==
{| class="wikitable" border="1"
! Break Reason
! Value
|-
| PANIC
| 0
|-
| ASSERT
| 1
|-
| USER
| 2
|}

== struct DebugEventInfo ==

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Event type
|-
| u32
| Thread ID (not used in all events)
|-
| u32[2]
| Unknown/padding
|-
| u32[6]
| Event-specific data (see below)
|}

{| class="wikitable" border="1"
! Event type
! Id
|-
| PROCESS
| 0
|-
| CREATE THREAD
| 1
|-
| EXIT THREAD
| 2
|-
| EXIT PROCESS
| 3
|-
| EXCEPTION
| 4
|-
| DLL LOAD
| 5
|-
| DLL UNLOAD
| 6
|-
| SCHEDULE IN
| 7
|-
| SCHEDULE OUT
| 8
|-
| SYSCALL IN
| 9
|-
| SYSCALL OUT
| 10
|-
| OUTPUT STRING
| 11
|-
| MAP
| 12
|}

=== PROCESS event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u64
| Program ID
|-
| char[8]
| Process name
|-
| u32
| Process ID
|-
| u32
| 0 = newly created process, 1 = attached process
|}

=== CREATE THREAD event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Creator thread ID
|-
| u32
| Base address (?)
|-
| u32
| Entrypoint
|}

=== EXIT THREAD/PROCESS events ===

A single u32 reason field is used.

Thread exit reasons:
{| class="wikitable" border="1"
! Reason
! Id
|-
| (None)
| 0
|-
| TERMINATE
| 1
|-
| EXIT PROCESS
| 2
|-
| TERMINATE PROCESS
| 3
|}

Process exit reasons:
{| class="wikitable" border="1"
! Reason
! Id
|-
| (None)
| 0
|-
| TERMINATE
| 1
|-
| UNHANDLED EXCEPTION
| 2
|}

=== EXCEPTION event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Exception type
|-
| u32
| Exception address
|-
| u32
| Argument (type-specific)
|}

Exception types:
{| class="wikitable" border="1"
! Reason
! Id
! Argument
|-
| UNDEFINED INSTRUCTION
| 0
| (None)
|-
| (Unknown)
| 1
| (None)
|-
| (Unknown, mem-related)
| 2
| Address
|-
| (Unknown, mem-related)
| 3
| Address
|-
| ATTACH BREAK
| 4
| (None)
|-
| BREAKPOINT
| 5
| (None)
|-
| USER BREAK
| 6
| User break type
|-
| DEBUGGER BREAK
| 7
| (None)
|-
| UNDEFINED SYSCALL
| 8
| Attempted syscall ID
|}

User break types:
{| class="wikitable" border="1"
! Reason
! Id
|-
| PANIC
| 0
|-
| ASSERT
| 1
|-
| USER
| 2
|}

=== SCHEDULER/SYSCALL IN/OUT events ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u64
| Clock tick
|-
| u32
| Syscall (only for SYSCALL events)
|}

=== OUTPUT STRING event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| String address
|-
| u32
| String size
|}

=== MAP event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Mapped address
|-
| u32
| Mapped size
|-
| u32
| MemoryPermission
|-
| u32
| MemoryState
|}

== typedef Handle ==

User-visible references to internal objects are represented by 32-bit integers called handles. Handles are only valid in the process they have been created in; hence, they cannot be exchanged between processes directly (the [[IPC]] functions provide a mean to copy handles to other processes, though).

There are a number of special-purpose handles, which provide easy access to information on objects in the current process:
{| class="wikitable" border="1"
! Handle
! Description
|-
| 0xFFFF8000
| Handle to the active thread
|-
| 0xFFFF8001
| Handle to the active process
|}

=svcSetHardwareBreakPoint=
This is essentially an interface for writing values to the debug-unit (B/W)RP registers. registerId range 0..5 = breakpoints(BRP0-5), 0x100..0x101 = watchpoints(WRP0-1), anything outside of these ranges will result in an error. This is used for both adding and removing/disabling breakpoints/watchpoints, hence the raw control value parameter.

Here the kernel sets bit15 in the DSCR, to enable monitor-mode debugging.

Regardless of whether this is for a BRP, when bit21 is set in the control input parameter(BRP type = contextID), the kernel will load the target process [[KProcess|contextID]] and use that internally for the value field. The target process is specified via a [[KDebug]] handle passed as the "value" parameter.

Lastly, the kernel disables the specified (B/W)RP, then writes the value parameter / loaded contextID to the (B/W)VR, then writes the input control value to the (B/W)CR.

= [[DMA]] =
The CTRSDK code for using svcStartInterProcessDma will execute svcBreak when svcStartInterProcessDma returns an error(except for certain error value(s)). Therefore on retail, triggering a svcStartInterProcessDma via a system-module which results in an error from svcStartInterProcessDma will result in the system-module terminating.

= Interrupt Handling =

BindInterrupt adds the given event handle to an internal list for the given interrupt ID. Whenever the given interrupt is triggered, the kernel's interrupt handler will signal all events in the list corresponding to that interrupt.

Applications hence can wait for specific interrupts to happen by calling WaitSynchronization(N) on the event handles.

It is unknown whether BindInterrupt may be used with non-event handles.

The set of existing ARM11 interrupts is listed on [[ARM11 Interrupts|this page]].

= Debugging =
DebugActiveProcess is used to attach to a process for debugging. This SVC can only be used when the target process' ARM11 descriptors stored in the exheader have the kernel flag for "Enable debug" set. Otherwise when that flag is clear, the kernel flags for the process using this SVC must have the "Force debug" flag set.

This SVC can only be used when a certain kernel state debug flag is non-zero(it's set to zero for retail).

= KernelSetState =
{| class="wikitable" border="1"
|-
! Type
! Enabled for the NATIVE_FIRM ARM11 kernel
! Enabled for the TWL_FIRM ARM11 kernel
! Description
|-
| 0
| Yes
| No
| This initializes the programID for launching [[FIRM]], then triggers launching [[FIRM]]. Param0 is unused. Param1 is the programID-low, and the programID-high is 0x00040138. Param2 is used only with the [[New_3DS]] kernel, pm-module uses value 0 with this. With New3DS kernel, it forces the programIDlow to be the New3DS NATIVE_FIRM, when the input programIDlow is for the Old3DS NATIVE_FIRM and Param2==0.
On New3DS, the kernel disables the additional New3DS cache hw prior to calling the firmlaunch function from the <handler for the KernelSetState-types called via funcptr>.
|-
| 1
| Yes
| Yes
| Unknown, does nothing with the TWL_FIRM ARM11 kernel.
|-
| 2
| Yes
| Yes
| Unknown.
On New3DS, the kernel disables the additional New3DS cache hw, when it's actually enabled, prior to executing the rest of the code from the <handler for the KernelSetState-types called via funcptr>.
|-
| 3
| Yes
| No
| This used for initializing the 0x1000-byte buffer used by the launched [[FIRM]]. Param2 is unused. When Param0 is value 1, this buffer is copied to the beginning of FCRAM at 0xF0000000, and Param1 is unused. When Param0 is value 0, this kernel buffer is mapped to process address Param1.
|-
| 4
| No
| Yes
| Param0-Param3 are unused. This unmaps(?) the following virtual memory by writing value physaddr(where physaddr base is 0x80000000) to the L1 MMU table entries: 0x00300000..0x04300000, 0x08000000..0x0FE00000, and 0x10000000..0xF8000000.
|-
| 5
| Yes
| Yes
| ?
|-
| 6
| Yes
| No
| Debug related?
|-
| 7
| Yes
| No
| This triggers an MCU (hard) reboot. Param0-3 are unused. This reboot is triggered via device address 0x4A on the second [[I2C]] bus (the MCU). Register address 0x20 is written to with value 4. This code will not return.
On New3DS, the kernel disables the additional New3DS cache hw prior to calling the reboot function from the <handler for the KernelSetState-types called via funcptr>.
|-
| 8
| Yes
| No
| Alternate FIRM launch code-path, with different [[PXI]] FIFO word constants. Usually not used. PTM-sysmodule can use this but it's unknown what exactly triggers that in PTM-sysmodule.
|-
| 9
| Yes, implemented at some point after system-version v4.5.
| ?
| Unknown
|-
| 10
| Yes
| ?
| ConfigureNew3DSCPU. Only available for the [[New_3DS]] kernel. The actual code for processing this runs under the <handler for the KernelSetState-types called via funcptr>, which runs on all ARM11 cores. Param0 = input value. Only bit0-1 are used here. Bit 0 enables higher core clock, and bit 1 enables additional (L2) cache. This configures the hardware [[PDN_Registers|register]] for the flags listed [[NCCH/Extended_Header#Flag1|here]], among other code which uses the MPCore private memory region registers.
|}

= GetSystemInfo =
{| class="wikitable" border="1"
! SystemInfoType value
! s32 param
! Description
|-
| 0
| 0
| This writes the total used memory size in the following memory regions to out: APPLICATION, SYSTEM, and BASE.
|-
| 0
| 1
| This writes the total used memory size in the APPLICATION memory region to out.
|-
| 0
| 2
| This writes the total used memory size in the SYSTEM memory region to out.
|-
| 0
| 3
| This writes the total used memory size in the BASE memory region to out.
|-
| 2
| Unused
| This writes the FCRAM memory [[Memory_Allocation#FCRAM_Region_Data|used by the kernel]] to out.
|-
| 25
| Unused
| This writes the total number of threads which were directly launched by the kernel, to out. No longer exists with some kernel version?
|-
| 26
| Unused
| This writes the total number of processes which were directly launched by the kernel, to out. For the NATIVE_FIRM/SAFE_MODE_FIRM ARM11 kernel, this is normally 5, for processes sm, fs, pm, loader, and pxi.
|}

= GetProcessInfo =
Input:
R0 = unused
R1 = Handle process
R2 = ProcessInfoType type

Output:
R0 = Result
R1 = output value lower word
R2 = output value upper word

{| class="wikitable" border="1"
! ProcessInfoType value
! Available since system version
! Description
|-
| 9-19
| [[8.0.0-18]]
| This only returns error 0xD8E007ED.
|-
| 20
| [[8.0.0-18]]
| low u32 = (0x20000000 - <LINEAR virtual-memory base for this process>). That is, the output value is the value which can be added to LINEAR memory vaddrs for converting to physical-memory addrs.
|-
| 21-23
| [[8.0.0-18]]
| This only returns error 0xE0E01BF4.
|}

= GetHandleInfo =

{| class="wikitable" border="1"
! HandleInfoType value
! Description
|-
| 0
| This returns the time in ticks the KProcess referenced by the handle was created. If a KProcess handle was not given, it will write whatever was in r5, r6 when the svc was called.
|-
| 1
| Get internal refcount-1 for kernel object (u32), and also a boolean if the refcount-1 is negative (u32).
|-
| 0x32107
| Returns (u64) 0.
|}

= svc7B Backdoor =
This saves SVC-mode SP+LR on the user-mode stack, then sets the SVC-mode SP to the user-mode SP. This then calls the specified code in SVC-mode. Once the called code returns, this pops the saved SP+LR off the stack for restoring the SVC-mode SP, then returns from the svc7b handler. Note that this svc7b handler does not disable IRQs, if any IRQs/context-switches occur while the SVC-mode SP is set to the user-mode one here, the ARM11-kernel will crash(which hangs the whole ARM11-side system).

= Kernel error-codes =
See [[Error codes]].

{| class="wikitable" border="1"
! Error-code value
! Description
|-
| 0x09401BFE
| Timeout occurred with svcWaitSynchronization*, when timeout is not ~0.
|-
| 0xC8601801
| No more unused/free synchronization objects left to use in a given object's linked list. (KEvent, KMutex, KTimer, KSemaphore, KAddressArbiter, KThread)
|-
| 0xC8601802
| No more unused/free KSharedMemory objects left to use in the KSharedMemory linked list - out of blocks
|-
| 0xC8601809
| No more unused/free KSessions left to use in the KSession linked list - out of sessions
|-
| 0xC860180A
| Not enough free memory available for memory allocation.
|-
| 0xC920181A
| The session was closed by the other process..
|-
| 0xD0401834
| Max connections to port have been exceeded
|-
| 0xD8609013
| Unknown, probably reslimit related?
|-
| 0xD88007FA
| Returned if no KObjectName object in the linked list of such objects matches the port name provided to the svc.
|-
| 0xD8E007ED
| This indicates that a value is outside of the enum being used.
|-
| 0xD8E007F1
| This error indicates Misaligned address.
|-
| 0xD8E007F7
| This error indicates that the input handle used with the SVC does not exist in the process handle-table, or that the handle kernel object type does not match the type used by the SVC.
|-
| 0xD9000402
| Invalid memory permissions for input/output buffers, for svcStartInterProcessDma.
|-
| 0xD9001814
| Failed unprivileged load or store - wrong permissions on memory
|-
| 0xD9001BF7
| This error is returned when the kernel retrieves a pointer to a kernel object, but the object type doesn't match the desired one.
|-
| 0xD92007EA
| This error is returned when a process attempts to use svcCreateMemoryBlock when the process memorytype is the application memorytype, and when addr=0.
|-
| 0xE0E01BF5
| This indicates an invalid address was used.
|-
| 0xF8C007F4
| Invalid type/param0-param3 input for svcKernelSetState. This is also returned for those syscalls marked as stubs.
|}

Memory Management

2016-08-06T11:02:30Z

Yuriks: /* Memory Mapping */

= Types and structures =

== enum MemoryOperation ==

{| class="wikitable" border="1"
! Memory operation
! Id
|-
| FREE
| 1
|-
| RESERVE
| 2
|-
| COMMIT
| 3
|-
| MAP
| 4
|-
| UNMAP
| 5
|-
| PROTECT
| 6
|-
| REGION APP
| 0x100
|-
| REGION SYSTEM
| 0x200
|-
| REGION BASE
| 0x300
|-
| LINEAR
| 0x10000
|}

The LINEAR memory-operation indicates that the mapped physical address is always MappedVAddr+0x0C000000, thus this memory can be used for hardware devices' DMA(such as the [[GPU]]). Addr0+size for this must be within the 0x14000000-0x1C000000 range when Addr0 is non-zero(Addr1 must be zero), Addr0 isn't actually used by svcControlMemory for mapping memory: Addr0 is not used by the kernel after doing address-range checks. The kernel determines what physical-address to use by allocating memory from FCRAM(about the same way as other memory), which is then used to determine the virtual-address.

[[8.0.0-18]] added a new memory mapping(0x30000000-0x38000000) for LINEAR memory, this replaces the original mapping for newer titles. The kernel uses the new mapping when the process memory-region is BASE, or when the process kernel-release-version field is >=0x022c(2.44 / system-version [[8.0.0-18]]).

The input mem-region value for svcControlMemory is only used(when non-zero) when the PID is value 1, for the [[FIRM]] ARM11 "loader" module.

== enum MemoryPermission ==

{| class="wikitable" border="1"
! Memory permission
! Id
|-
| NONE
| 0
|-
| R
| 1
|-
| W
| 2
|-
| RW
| 3
|-
| X
| 4
|-
| RX
| 5
|-
| WX
| 6
|-
| RWX
| 7
|-
| DONTCARE
| 0x10000000
|}

== enum MemoryState ==
{| class="wikitable" border="1"
! Memory state flags
! Value
|-
| FREE
| 0
|-
| RESERVED
| 1
|-
| IO
| 2
|-
| STATIC
| 3
|-
| CODE
| 4
|-
| PRIVATE
| 5
|-
| SHARED
| 6
|-
| CONTINUOUS
| 7
|-
| ALIASED
| 8
|-
| ALIAS
| 9
|-
| ALIAS CODE
| 10
|-
| LOCKED
| 11
|}

== struct MemoryInfo ==
{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Base process virtual address
|-
| u32
| Size
|-
| u32
| Permission
|-
| enum MemoryState
| State
|}

== enum PageFlags ==
{| class="wikitable" border="1"
! Page flags
! Bit
|-
| LOCKED
| 0
|-
| CHANGED
| 1
|}

== struct PageInfo ==
{| class="wikitable" border="1"
! Type
! Field
|-
| PageFlags (u32)
| Flags
|}

= Memory Mapping =
ControlMemory and MapMemoryBlock can be used to map memory pages, these two SVCs only support mapping execute-never R/W pages. The input permissions parameter for these SVCs must therefore be <=3, where value zero is used when un-mapping memory. Furthermore it appears that only regular heap pages can be mirrored (it won't work for TLS, stack, .data, .text, for example).

Bitmask 0xF00 for ControlMemory parameter MemoryType is the memory-type, when this is zero the memory-type is loaded from the kernel flags stored in the exheader ARM11 kernel descriptors, for the process using the SVC.

ControlMemory parameter MemoryType with value 0x10003 is used for mapping the GSP [[Memory_layout|heap]]. The low 8-bits are the type: 1 is for un-mapping memory, 3 for mapping memory. Type4 is used to mirror the RW memory at Addr1, to Addr0. Type4 will return an error if Addr1 is located in read-only memory. Addr1 is not used for type1 and type3.

The ARM11 kernel does not allow processes to create shared memory blocks via svcCreateMemoryBlock, when the process memorytype (from the kernel flags stored in the exheader kernel descriptor) is the application memorytype, and when addr=0. When the memorytype is not the application memorytype and addr=0, the kernel allocates new memory for the calling process and turns it into a shared memory block. When addr is non-zero, it must be located in memory which is already mapped. Furthermore, it appears that only regular heap pages (allocated using svcControlMemory op=COMMIT) are accepted as valid addrs.

ControlProcessMemory maps memory in the specified process, this is the only SVC which allows mapping executable memory. Format of the permissions field for memory mapping SVCs: bit0=R, bit1=W, bit2=X. Type6 sets the Addr0 memory permissions to the input permissions, for already mapped memory. Type is the MemoryOperation enum, without the memory-type/memory-region. ControlProcessMemory only supports type4, type5, and type6. ControlProcessMemory does not support using the current KProcess handle alias.

<code>'''MapProcessMemory'''(Handle process, u32 destAddr, u32 limit)</code> maps memory from the given process into the current process. First <code>min(limit, 0x3F00000)</code> bytes are mapped starting from <code>0x00100000</code> in the source process to <code>destAddr</code> in the current process. Then <code>min(limit - 0x7F00000, 0x6000000)</code> bytes (if more than 0) are mapped from <code>0x08000000</code> in the source process to <code>destAddr + 0x7F00000</code> in the current process. Another way to view this is that it is overlaying the two ranges <code>[0x0010_0000; 0x0400_0000]</code> and <code>[0x0800_0000; 0x0E00_0000]</code> from the source process onto <code>[destAddr - 0x100000; destAddr + limit]</code> in the current process, truncating whatever part of the mapping that doesn't fit. This SVC used by [[RO Services]] to map the program's code and heap into ro. Memory mapped by MapProcessMemory is unmapped by UnmapProcessMemory.

Note that with the MAP MemoryOperation, the kernel will refuse to MAP memory for the specified addr1, when addr1 was already used with another MAP operation as addr1. The kernel also doesn't allow memory to be freed via the FREE MemoryOperation, when other virtual-memory is mapped to this same memory(when the MAP MemoryOperation was used with this memory with addr1).

= How The Kernel Allocates And Tracks Memory =

== MemoryBlockHeader ==

Size: 0xC-bytes(?) pre-v11.0, 0x18-bytes starting with v11.0.

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| u32
| Size in pages
|-
| 0x4
| MemoryBlockHeader*
| Next
|-
| 0x8
| MemoryBlockHeader*
| Prev
|-
| 0xC
| MemoryBlockHeader*
| Pointer to the current memchunk. Added with v11.0?
|-
| 0x10
| u32
| Nonce, doesn't seem to be read at all except during MAC calculation. Added with v11.0. Used with the new heap [[11.0.0-33|security]] feature. A kernel state field is copied to this field before calculating the MAC. Once done, that kernel state field is subtracted by the value of the calculated MAC stored below. Since this kernel state field is initially 0x0, this field for the FCRAM APPLICATION+0 MemoryBlockHeader during kernel boot is set to 0x0.
|-
| 0x14
| u32
| MAC calculated over rest of struct. Added with v11.0. Used with the new heap [[11.0.0-33|security]] feature.
|}

== RegionDescriptor ==

Size: 0x10-bytes pre-[[11.0.0-33|11.0.0-X]], 0x20-bytes starting with [[11.0.0-33|11.0.0-X]].

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| MemoryBlockHeader*
|
|-
| 0x4
| MemoryBlockHeader*
|
|-
| 0x8
| u32
| Region start
|-
| 0xC
| u32
| Region size
|-
| 0x10
| 0x10-byte block.
| This is the "key" used with the kernel heap MAC implemented with [[11.0.0-33|11.0.0-X]].
|}

== FCRAM Region Descriptor ==

Size: 0x50-bytes pre-[[11.0.0-33|11.0.0-X]], 0x80-bytes starting with [[11.0.0-33|11.0.0-X]].

X = RegionDescriptor_size*3.

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| RegionDescriptor
| RegionDescriptor for app memory
|-
| RegionDescriptor_size*1
| RegionDescriptor
| RegionDescriptor for sys memory
|-
| RegionDescriptor_size*2
| RegionDescriptor
| RegionDescriptor for base memory
|-
| X + 0x0
| u32
| Ptr to start of FCRAM region descriptor
|-
| X + 0x4
| u32
| FCRAM start
|-
| X + 0x8
| u32
| FCRAM size in pages
|-
| X + 0xC
| u32
| Base memory start in FCRAM
|-
| X + 0x10
| u32
| Count of physical FCRAM used by the kernel, in bytes. (used by [[SVC|svcGetSystemInfo]])
|-
| X + 0x14
| u32
| ?
|-
| X + 0x18
| KThread*
| Thread operating on region data
|-
| X + 0x1C
| s16
| Error info for thread listed above
|-
| X + 0x1E
| u16
| Alignment
|}

== Kernel Region Descriptor ==

Memory Management

2016-08-06T10:58:55Z

Yuriks: /* Memory Mapping */

= Types and structures =

== enum MemoryOperation ==

{| class="wikitable" border="1"
! Memory operation
! Id
|-
| FREE
| 1
|-
| RESERVE
| 2
|-
| COMMIT
| 3
|-
| MAP
| 4
|-
| UNMAP
| 5
|-
| PROTECT
| 6
|-
| REGION APP
| 0x100
|-
| REGION SYSTEM
| 0x200
|-
| REGION BASE
| 0x300
|-
| LINEAR
| 0x10000
|}

The LINEAR memory-operation indicates that the mapped physical address is always MappedVAddr+0x0C000000, thus this memory can be used for hardware devices' DMA(such as the [[GPU]]). Addr0+size for this must be within the 0x14000000-0x1C000000 range when Addr0 is non-zero(Addr1 must be zero), Addr0 isn't actually used by svcControlMemory for mapping memory: Addr0 is not used by the kernel after doing address-range checks. The kernel determines what physical-address to use by allocating memory from FCRAM(about the same way as other memory), which is then used to determine the virtual-address.

[[8.0.0-18]] added a new memory mapping(0x30000000-0x38000000) for LINEAR memory, this replaces the original mapping for newer titles. The kernel uses the new mapping when the process memory-region is BASE, or when the process kernel-release-version field is >=0x022c(2.44 / system-version [[8.0.0-18]]).

The input mem-region value for svcControlMemory is only used(when non-zero) when the PID is value 1, for the [[FIRM]] ARM11 "loader" module.

== enum MemoryPermission ==

{| class="wikitable" border="1"
! Memory permission
! Id
|-
| NONE
| 0
|-
| R
| 1
|-
| W
| 2
|-
| RW
| 3
|-
| X
| 4
|-
| RX
| 5
|-
| WX
| 6
|-
| RWX
| 7
|-
| DONTCARE
| 0x10000000
|}

== enum MemoryState ==
{| class="wikitable" border="1"
! Memory state flags
! Value
|-
| FREE
| 0
|-
| RESERVED
| 1
|-
| IO
| 2
|-
| STATIC
| 3
|-
| CODE
| 4
|-
| PRIVATE
| 5
|-
| SHARED
| 6
|-
| CONTINUOUS
| 7
|-
| ALIASED
| 8
|-
| ALIAS
| 9
|-
| ALIAS CODE
| 10
|-
| LOCKED
| 11
|}

== struct MemoryInfo ==
{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Base process virtual address
|-
| u32
| Size
|-
| u32
| Permission
|-
| enum MemoryState
| State
|}

== enum PageFlags ==
{| class="wikitable" border="1"
! Page flags
! Bit
|-
| LOCKED
| 0
|-
| CHANGED
| 1
|}

== struct PageInfo ==
{| class="wikitable" border="1"
! Type
! Field
|-
| PageFlags (u32)
| Flags
|}

= Memory Mapping =
ControlMemory and MapMemoryBlock can be used to map memory pages, these two SVCs only support mapping execute-never R/W pages. The input permissions parameter for these SVCs must therefore be <=3, where value zero is used when un-mapping memory. Furthermore it appears that only regular heap pages can be mirrored (it won't work for TLS, stack, .data, .text, for example).

Bitmask 0xF00 for ControlMemory parameter MemoryType is the memory-type, when this is zero the memory-type is loaded from the kernel flags stored in the exheader ARM11 kernel descriptors, for the process using the SVC.

ControlMemory parameter MemoryType with value 0x10003 is used for mapping the GSP [[Memory_layout|heap]]. The low 8-bits are the type: 1 is for un-mapping memory, 3 for mapping memory. Type4 is used to mirror the RW memory at Addr1, to Addr0. Type4 will return an error if Addr1 is located in read-only memory. Addr1 is not used for type1 and type3.

The ARM11 kernel does not allow processes to create shared memory blocks via svcCreateMemoryBlock, when the process memorytype (from the kernel flags stored in the exheader kernel descriptor) is the application memorytype, and when addr=0. When the memorytype is not the application memorytype and addr=0, the kernel allocates new memory for the calling process and turns it into a shared memory block. When addr is non-zero, it must be located in memory which is already mapped. Furthermore, it appears that only regular heap pages (allocated using svcControlMemory op=COMMIT) are accepted as valid addrs.

ControlProcessMemory maps memory in the specified process, this is the only SVC which allows mapping executable memory. Format of the permissions field for memory mapping SVCs: bit0=R, bit1=W, bit2=X. Type6 sets the Addr0 memory permissions to the input permissions, for already mapped memory. Type is the MemoryOperation enum, without the memory-type/memory-region. ControlProcessMemory only supports type4, type5, and type6. ControlProcessMemory does not support using the current KProcess handle alias.

<code>'''MapProcessMemory'''(Handle process, u32 destAddr, u32 limit)</code> maps memory from the given process into the current process. First <code>min(limit, 0x3F00000)</code> bytes are mapped starting from <code>0x00100000</code> in the source process to <code>destAddr</code> in the current process. Then <code>min(limit - 0x7F00000, 0x6000000)</code> bytes (if more than 0) are mapped from <code>0x08000000</code> in the source process to <code>destAddr + 0x7F00000</code> in the current process. Another way to view this is that it is overlaying the two ranges <code>[0x0010_0000; 0x0400_0000]</code> and <code>[0x0800_0000; 0x0E00_0000]</code> from the source process onto <code>destAddr - 0x100000</code> in the current process, but only covering up to <code>limit + 0x100000</code> bytes. This is used by [[RO Services]] to map the program's code and heap into ro. Memory mapped by MapProcessMemory is unmapped by UnmapProcessMemory.

Note that with the MAP MemoryOperation, the kernel will refuse to MAP memory for the specified addr1, when addr1 was already used with another MAP operation as addr1. The kernel also doesn't allow memory to be freed via the FREE MemoryOperation, when other virtual-memory is mapped to this same memory(when the MAP MemoryOperation was used with this memory with addr1).

= How The Kernel Allocates And Tracks Memory =

== MemoryBlockHeader ==

Size: 0xC-bytes(?) pre-v11.0, 0x18-bytes starting with v11.0.

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| u32
| Size in pages
|-
| 0x4
| MemoryBlockHeader*
| Next
|-
| 0x8
| MemoryBlockHeader*
| Prev
|-
| 0xC
| MemoryBlockHeader*
| Pointer to the current memchunk. Added with v11.0?
|-
| 0x10
| u32
| Nonce, doesn't seem to be read at all except during MAC calculation. Added with v11.0. Used with the new heap [[11.0.0-33|security]] feature. A kernel state field is copied to this field before calculating the MAC. Once done, that kernel state field is subtracted by the value of the calculated MAC stored below. Since this kernel state field is initially 0x0, this field for the FCRAM APPLICATION+0 MemoryBlockHeader during kernel boot is set to 0x0.
|-
| 0x14
| u32
| MAC calculated over rest of struct. Added with v11.0. Used with the new heap [[11.0.0-33|security]] feature.
|}

== RegionDescriptor ==

Size: 0x10-bytes pre-[[11.0.0-33|11.0.0-X]], 0x20-bytes starting with [[11.0.0-33|11.0.0-X]].

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| MemoryBlockHeader*
|
|-
| 0x4
| MemoryBlockHeader*
|
|-
| 0x8
| u32
| Region start
|-
| 0xC
| u32
| Region size
|-
| 0x10
| 0x10-byte block.
| This is the "key" used with the kernel heap MAC implemented with [[11.0.0-33|11.0.0-X]].
|}

== FCRAM Region Descriptor ==

Size: 0x50-bytes pre-[[11.0.0-33|11.0.0-X]], 0x80-bytes starting with [[11.0.0-33|11.0.0-X]].

X = RegionDescriptor_size*3.

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| RegionDescriptor
| RegionDescriptor for app memory
|-
| RegionDescriptor_size*1
| RegionDescriptor
| RegionDescriptor for sys memory
|-
| RegionDescriptor_size*2
| RegionDescriptor
| RegionDescriptor for base memory
|-
| X + 0x0
| u32
| Ptr to start of FCRAM region descriptor
|-
| X + 0x4
| u32
| FCRAM start
|-
| X + 0x8
| u32
| FCRAM size in pages
|-
| X + 0xC
| u32
| Base memory start in FCRAM
|-
| X + 0x10
| u32
| Count of physical FCRAM used by the kernel, in bytes. (used by [[SVC|svcGetSystemInfo]])
|-
| X + 0x14
| u32
| ?
|-
| X + 0x18
| KThread*
| Thread operating on region data
|-
| X + 0x1C
| s16
| Error info for thread listed above
|-
| X + 0x1E
| u16
| Alignment
|}

== Kernel Region Descriptor ==

GPU/Internal Registers

2016-03-06T03:06:53Z

Yuriks: /* GPUREG_DEPTH_COLOR_MASK */ Add information about "Depth test enable" not disabling depth writes.

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-30
| Number of extra parameters (may be zero)
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X
|-
| 16-25
| unsigned, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1)
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = not perspective, 1 = perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U2
|-
| 2
| V
|-
| 3
| V2
|-
| 4
| U + V
|-
| 5
| U2 + V2
|-
| 6
| sqrt(U2*U2 + V2*V2)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-10
| 0x60
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset
|-
| 8-31
| 0xE0C080
|}

This register is used to set the procedural texture unit's offset.

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| fixed1.0.7, Red difference between current and next color table elements
|-
| 8-15
| fixed1.0.7, Green difference between current and next color table elements
|-
| 16-23
| fixed1.0.7, Blue difference between current and next color table elements
|-
| 24-31
| fixed1.0.7, Alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

Equation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|}

This register configures gas light shading in the line-of-sight direction.

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|}

This register is used to configure the gas depth direction attenuation proportion.

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20-22
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = false, 1 = true)
|-
| 1
| unsigned, Boolean register b1 value (0 = false, 1 = true)
|-
| 2
| unsigned, Boolean register b2 value (0 = false, 1 = true)
|-
| 3
| unsigned, Boolean register b3 value (0 = false, 1 = true)
|-
| 4
| unsigned, Boolean register b4 value (0 = false, 1 = true)
|-
| 5
| unsigned, Boolean register b5 value (0 = false, 1 = true)
|-
| 6
| unsigned, Boolean register b6 value (0 = false, 1 = true)
|-
| 7
| unsigned, Boolean register b7 value (0 = false, 1 = true)
|-
| 8
| unsigned, Boolean register b8 value (0 = false, 1 = true)
|-
| 9
| unsigned, Boolean register b9 value (0 = false, 1 = true)
|-
| 10
| unsigned, Boolean register b10 value (0 = false, 1 = true)
|-
| 11
| unsigned, Boolean register b11 value (0 = false, 1 = true)
|-
| 12
| unsigned, Boolean register b12 value (0 = false, 1 = true)
|-
| 13
| unsigned, Boolean register b13 value (0 = false, 1 = true)
|-
| 14
| unsigned, Boolean register b14 value (0 = false, 1 = true)
|-
| 15
| unsigned, Boolean register b15 value (0 = false, 1 = true)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

DSP:RegisterInterruptEvents

2016-02-15T11:29:42Z

Yuriks:

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x00150082]
|-
| 1
| Interrupt
|-
| 2
| Channel
|-
| 3
| 0x0
|-
| 4
| Event handle (0 = unregister the event that was previous registered)
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x00150040]
|-
| 1
| Result code
|}

=Description=
Application should unregister the event by setting handle to zero. If the session was closed before the event was unregistered, it will cause a handle leak in DSP process.

DSP can hold up to 6 concurrent registrations. More than that will cause registration to fail.

GPU/Shader Instruction Set

2016-01-25T03:36:38Z

Yuriks: /* Instructions */ Confirmed JMPU invert bit

[[Category:GPU]]

== Overview ==
A compiled shader binary is comprised of two parts : the main instruction sequence and the operand descriptor table. These are both sent to the GPU around the same time but using separate [[GPU/Internal_Registers|GPU Commands]]. Instructions (such as format 1 instruction) may reference operand descriptors. When such is the case, the operand descriptor ID is the offset, in words, of the descriptor within the table.
Both instructions and descriptors are coded in little endian.
Basic implementations of the following specification can be found at [https://github.com/smealum/aemstro] and [https://github.com/neobrain/nihstro].
The instruction set seems to have been heavily inspired by Microsoft's vs_3_0 [http://msdn.microsoft.com/en-us/library/windows/desktop/bb172938%28v=vs.85%29.aspx] and the Direct3D shader code [https://msdn.microsoft.com/en-us/library/windows/hardware/ff552891%28v=vs.85%29.aspx].
Please note that this page is being written as the instruction set is reverse engineered; as such it may very well contain mistakes.

Debug information found in the code.bin of "Ironfall: Invasion" suggests that there may not be more than 512 instructions and 128 operand descriptors in a shader.

== Nomenclature ==

* opcode names with I appended to them are the same as their non-I version, except they use the inverted instruction format, giving 7 bits to SRC2 (and access to uniforms) and 5 bits to SRC1

* opcode names with U appended to them are the same as their non-U version, except they are executed conditionally based on the value of a uniform boolean.

* opcode names with C appended to them are the same as their non-C version, except they are executed conditionally based on a logical expression specified in the instruction.

== Instruction formats ==

Format 1 : (used for register operations)
{| class="wikitable" border="1"
|-
! Offset
! Size (bits)
! Description
|-
| 0x0
| 0x7
| Operand descriptor ID (DESC)
|-
| 0x7
| 0x5
| Source 2 register (SRC2)
|-
| 0xC
| 0x7
| Source 1 register (SRC1)
|-
| 0x13
| 0x2
| Address register index for SRC1 (IDX_1)
|-
| 0x15
| 0x5
| Destination register (DST)
|-
| 0x1A
| 0x6
| Opcode
|}

Format 1i : (used for register operations)
{| class="wikitable" border="1"
|-
! Offset
! Size (bits)
! Description
|-
| 0x0
| 0x7
| Operand descriptor ID (DESC)
|-
| 0x7
| 0x7
| Source 2 register (SRC2)
|-
| 0xE
| 0x5
| Source 1 register (SRC1)
|-
| 0x13
| 0x2
| Address register index for SRC2 (IDX_2)
|-
| 0x15
| 0x5
| Destination register (DST)
|-
| 0x1A
| 0x6
| Opcode
|}

Format 1u : (used for unary register operations)
{| class="wikitable" border="1"
|-
! Offset
! Size (bits)
! Description
|-
| 0x0
| 0x7
| Operand descriptor ID (DESC)
|-
| 0xC
| 0x7
| Source 1 register (SRC1)
|-
| 0x13
| 0x2
| Address register index for SRC1 (IDX_1)
|-
| 0x15
| 0x5
| Destination register (DST)
|-
| 0x1A
| 0x6
| Opcode
|}

Format 1c : (used for comparison operations)
{| class="wikitable" border="1"
|-
! Offset
! Size (bits)
! Description
|-
| 0x0
| 0x7
| Operand descriptor ID (DESC)
|-
| 0x7
| 0x7
| Source 1 register (SRC1)
|-
| 0xE
| 0x5
| Source 2 register (SRC2)
|-
| 0x13
| 0x2
| Address register index for SRC1 (IDX_1)
|-
| 0x15
| 0x3
| Comparison operator for Y (CMPY)
|-
| 0x18
| 0x3
| Comparison operator for X (CMPX)
|-
| 0x1B
| 0x5
| Opcode
|}

Format 2 : (used for flow control instructions)
{| class="wikitable" border="1"
|-
! Offset
! Size (bits)
! Description
|-
| 0x0
| 0x8
| Number of instructions (NUM)
|-
| 0xA
| 0xC
| Destination offset (in words) (DST)
|-
| 0x16
| 0x2
| Condition boolean operator (CONDOP)
|-
| 0x18
| 0x1
| Y reference bit (REFY)
|-
| 0x19
| 0x1
| X reference bit (REFX)
|-
| 0x1A
| 0x6
| Opcode
|}

Format 3 : (used for uniform-based conditional flow control instructions)
{| class="wikitable" border="1"
|-
! Offset
! Size (bits)
! Description
|-
| 0x0
| 0x8
| Number of instructions ? (NUM)
|-
| 0xA
| 0xC
| Destination offset (in words) (DST)
|-
| 0x16
| 0x4
| Uniform ID (BOOL/INT)
|-
| 0x1A
| 0x6
| Opcode
|}

Format 4 : (used for SETEMIT)
{| class="wikitable" border="1"
|-
! Offset
! Size (bits)
! Description
|-
| 0x16
| 0x1
| Winding flag (FLAG_WINDING)
|-
| 0x17
| 0x1
| Primitive emit flag (FLAG_PRIMEMIT)
|-
| 0x18
| 0x2
| Vertex ID (VTXID)
|-
| 0x1A
| 0x6
| Opcode
|}

Format 5 : (used for MAD)
{| class="wikitable" border="1"
|-
! Offset
! Size (bits)
! Description
|-
| 0x0
| 0x5
| Operand descriptor ID (DESC)
|-
| 0x5
| 0x5
| Source 3 register (SRC3)
|-
| 0xA
| 0x7
| Source 2 register (SRC2)
|-
| 0x11
| 0x7
| Source 1 register (SRC1)
|-
| 0x18
| 0x5
| Destination register (DST)
|-
| 0x1D
| 0x3
| Opcode
|}

Format 5i : (used for MADI)
{| class="wikitable" border="1"
|-
! Offset
! Size (bits)
! Description
|-
| 0x0
| 0x5
| Operand descriptor ID (DESC)
|-
| 0x5
| 0x7
| Source 3 register (SRC3)
|-
| 0xC
| 0x5
| Source 2 register (SRC2)
|-
| 0x11
| 0x7
| Source 1 register (SRC1)
|-
| 0x18
| 0x5
| Destination register (DST)
|-
| 0x1D
| 0x3
| Opcode
|}

== Instructions ==
Unless noted otherwise, SRC1 and SRC2 refer to their respectively indexed float[4] registers (after swizzling). Similarly, DST refers to its indexed register modulo destination component masking, i.e. an expression like DST=SRC1 might actually just set DST.y to SRC1.y.

{| class="wikitable" border="1"
|-
! Opcode
! Format
! Name
! Description
|-
| 0x00
| 1
| ADD
| Adds two vectors component by component; DST[i] = SRC1[i]+SRC2[i] for all i
|-
| 0x01
| 1
| DP3
| Computes dot product on 3-component vectors; DST = SRC1.SRC2
|-
| 0x02
| 1
| DP4
| Computes dot product on 4-component vectors; DST = SRC1.SRC2
|-
| 0x03
| 1
| DPH
| Computes dot product on a 3-component vector with 1.0 appended to it and a 4-component vector; DST = SRC1.SRC2 (with SRC1 homogenous)
|-
| 0x04
| 1
| ???
| ?
|-
| 0x05
| 1u
| EX2
| Computes SRC1's first component exponent with base 2; DST[i] = EXP2(SRC1[0]) for all i
|-
| 0x06
| 1u
| LG2
| Computes SRC1's first component logarithm with base 2; DST[i] = LOG2(SRC1[0]) for all i
|-
| 0x07
| 1u
| ???
| ?
|-
| 0x08
| 1
| MUL
| Multiplies two vectors component by component; DST[i] = SRC1[i].SRC2[i] for all i
|-
| 0x09
| 1
| SGE
| Sets output if SRC1 is greater than or equal to SRC2; DST[i] = (SRC1[i] >= SRC2[i]) ? 1.0 : 0.0 for all i
|-
| 0x0A
| 1
| SLT
| Sets output if SRC1 is strictly less than SRC2; DST[i] = (SRC1[i] < SRC2[i]) ? 1.0 : 0.0 for all i
|-
| 0x0B
| 1u
| FLR
| Computes SRC1's floor component by component; DST[i] = FLOOR(SRC1[i]) for all i
|-
| 0x0C
| 1
| MAX
| Takes the max of two vectors, component by component; DST[i] = MAX(SRC1[i], SRC2[i]) for all i
|-
| 0x0D
| 1
| MIN
| Takes the min of two vectors, component by component; DST[i] = MIN(SRC1[i], SRC2[i]) for all i
|-
| 0x0E
| 1u
| RCP
| Computes the reciprocal of the vector's first component; DST[i] = 1/SRC1[0] for all i
|-
| 0x0F
| 1u
| RSQ
| Computes the reciprocal of the square root of the vector's first component; DST[i] = 1/sqrt(SRC1[0]) for all i
|-
| 0x10
| ?
| ???
| ?
|-
| 0x11
| ?
| ???
| ?
|-
| 0x12
| 1u
| MOVA
| Move to address register; Casts the float uniform given by SRC1 to an integer (truncating the fractional part) and assigns the result to (a0.x, a0.y, _, _), respecting the destination component mask.
|-
| 0x13
| 1u
| MOV
| Moves value from one register to another; DST = SRC1.
|-
| 0x14
| ?
| ???
| ?
|-
| 0x15
| ?
| ???
| ?
|-
| 0x16
| ?
| ???
| ?
|-
| 0x17
| ?
| ???
| ?
|-
| 0x18
| 1i
| DPHI
| Computes dot product on a 3-component vector with 1.0 appended to it and a 4-component vector; DST = SRC1.SRC2 (with SRC1 homogenous)
|-
| 0x19
| 1i
| ???
| ?
|-
| 0x1A
| 1i
| SGEI
| Sets output if SRC1 is greater than or equal to SRC2; DST[i] = (SRC1[i] >= SRC2[i]) ? 1.0 : 0.0 for all i
|-
| 0x1B
| 1i
| SLTI
| Sets output if SRC1 is strictly less than SRC2; DST[i] = (SRC1[i] < SRC2[i]) ? 1.0 : 0.0 for all i
|-
| 0x1C
| ?
| ???
| ?
|-
| 0x1D
| ?
| ???
| ?
|-
| 0x1E
| ?
| ???
| ?
|-
| 0x1F
| ?
| ???
| ?
|-
| 0x20
| ?
| ???
| ?
|-
| 0x21
| 0
| NOP
| Does literally nothing.
|-
| 0x22
| 0
| END
| Signals the shader unit that processing for this vertex/primitive is done.
|-
| 0x23
| 2
| BREAKC
| If condition (see [[#Conditions|below]] for details) is true, then breaks out of LOOP block.
|-
| 0x24
| 2
| CALL
| Jumps to DST and executes instructions until it reaches DST+NUM instructions
|-
| 0x25
| 2
| CALLC
| If condition (see [[#Conditions|below]] for details) is true, then jumps to DST and executes instructions until it reaches DST+NUM instructions, else does nothing.
|-
| 0x26
| 3
| CALLU
| Jumps to DST and executes instructions until it reaches DST+NUM instructions if BOOL is true
|-
| 0x27
| 3
| IFU
| If condition BOOL is true, then executes instructions until DST, then jumps to DST+NUM; else, jumps to DST.
|-
| 0x28
| 2
| IFC
| If condition (see [[#Conditions|below]] for details) is true, then executes instructions until DST, then jumps to DST+NUM; else, jumps to DST
|-
| 0x29
| 3
| LOOP
| Loops over the code between itself and DST (inclusive), performing INT.x+1 iterations in total. First, aL is initialized to INT.y. After each iteration, aL is incremented by INT.z.
|-
| 0x2A
| 0 (no param)
| EMIT
| (geometry shader only) Emits a vertex (and primitive if FLAG_PRIMEMIT was set in the corresponding SETEMIT). SETEMIT must be called before this.
|-
| 0x2B
| 4
| SETEMIT
| (geometry shader only) Sets VTXID, FLAG_WINDING and FLAG_PRIMEMIT for the next EMIT instruction. VTXID is the ID of the vertex about to be emitted within the primitive, while FLAG_PRIMEMIT is zero if we are just emitting a single vertex and non-zero if are emitting a vertex and primitive simultaneously. FLAG_WINDING controls the output primitive's winding. Note that the output vertex buffer (which holds 4 vertices) is '''not''' cleared when the primitive is emitted, meaning that vertices from the previous primitive can be reused for the current one. (this is still a working hypothesis and unconfirmed)
|-
| 0x2C
| 2
| JMPC
| If condition (see [[#Conditions|below]] for details) is true, then jumps to DST, else does nothing.
|-
| 0x2D
| 3
| JMPU
| If condition BOOL is true, then jumps to DST, else does nothing. Having bit 0 of NUM = 1 will invert the test, jumping if BOOL is false instead.
|-
| 0x2E-0x2F
| 1c
| CMP
| Sets booleans cmp.x and cmp.y based on the operand's x and y components and the CMPX and CMPY comparison operators respectively. See [[#Comparison_operator|below]] for details about operators. It's unknown whether CMP respects the destination component mask or not.
|-
| 0x30-0x37
| 5i
| MADI
| Multiplies two vectors and adds a third one component by component; DST[i] = SRC3[i] + SRC2[i].SRC1[i] for all i
|-
| 0x38-0x3F
| 5
| MAD
| Multiplies two vectors and adds a third one component by component; DST[i] = SRC3[i] + SRC2[i].SRC1[i] for all i
|}

== Operand descriptors ==
Sizes below are in bits, not bytes.

{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| 0x0
| 0x4
| Destination component mask. Bit 3 = x, 2 = y, 1 = z, 0 = w.
|-
| 0x4
| 0x1
| Source 1 negation bit
|-
| 0x5
| 0x8
| Source 1 component selector
|-
| 0xD
| 0x1
| Source 2 negation bit
|-
| 0xE
| 0x8
| Source 2 component selector
|-
| 0x16
| 0x1
| Source 3 negation bit
|-
| 0x17
| 0x8
| Source 3 component selector
|}

Component selector :
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| 0x0
| 0x2
| Component 3 value
|-
| 0x2
| 0x2
| Component 2 value
|-
| 0x4
| 0x2
| Component 1 value
|-
| 0x6
| 0x2
| Component 0 value
|}

{| class="wikitable" border="1"
|-
! Value
! Component
|-
| 0x0
| x
|-
| 0x1
| y
|-
| 0x2
| z
|-
| 0x3
| w
|}

The component selector enables swizzling. For example, component selector 0x1B is equivalent to .xyzw, while 0x55 is equivalent to .yyyy.

Depending on the current shader opcode, source components are disabled implicitly by setting the destination component mask. For example, ADD o0.xy, r0.xyzw, r1.xyzw will not make use of r0's or r1's z/w components, while DP4 o0.xy, r0.xyzw, r1.xyzw will use all input components regardless of the used destination component mask.

== Relative addressing ==

There are 3 address registers: a0.x, a0.y and aL (loop counter). For format 1 instructions, when IDX != 0, the value of the corresponding address register is added to SRC1's value. For example, if IDX = 2, a0.y = 3 and SRC1 = c8, then instead SRC1+a0.y = c11 will be used for the instruction.

a0.x and a0.y are set manually through the MOVA instruction by rounding a float value to integer precision. Hence, they may take negative values.

aL can only be set indirectly by the LOOP instruction. It is still accessible and valid after exiting a LOOP block, though.

== Comparison operator ==

{| class="wikitable" border="1"
|-
! CMPX/CMPY raw value
! Operator name
! Expression
|-
| 0x0
| EQ
| src1 == src2
|-
| 0x1
| NE
| src1 != src2
|-
| 0x2
| LT
| src1 < src2
|-
| 0x3
| LE
| src1 <= src2
|-
| 0x4
| GT
| src1 > src2
|-
| 0x5
| GE
| src1 >= src2
|-
| 0x6
| ??
| true ?
|-
| 0x7
| ??
| true ?
|}

6 and 7 seem to always return true.

== Conditions ==

A number of format 2 instructions are executed conditionally. These conditions are based on two boolean registers which can be set with CMP : cmp.x and cmp.y.

Conditional instructions include 3 parameters : CONDOP, REFX and REFY. REFX and REFY are reference values which are tested for equality against cmp.x and cmp.y, respectively. CONDOP describes how the final truth value is constructed from the results of the two tests. There are four conditional expression formats :

{| class="wikitable" border="1"
|-
! CONDOP raw value
! Expression
! Description
|-
| 0x0
| <nowiki>cmp.x == REFX || cmp.y == REFY</nowiki>
| OR
|-
| 0x1
| <nowiki>cmp.x == REFX && cmp.y == REFY</nowiki>
| AND
|-
| 0x2
| cmp.x == REFX
| X
|-
| 0x3
| cmp.y == REFY
| Y
|}

== Registers ==
Input attribute registers (v0-v7?) store the per-vertex data given by the CPU and hence are read-only.

Output attribute registers (o0-o6) hold the data to be passed to the later GPU stages and are write-only. Each of the output attribute register components is assigned a semantic by setting the corresponding [[GPU_Internal_Registers]].

Uniform registers hold user-specified data which is constant throughout all processed vertices. There are 96 float[4] uniform registers (c0-c95), eight boolean registers (b0-b7), and four int[4] registers (i0-i3).

Temporary registers (r0-r15) can be used for intermediate calculations and can both be read and written.

Many shader instructions which take float arguments have only 5 bits available for the second argument. They may hence only refer to input attributes or temporary registers. In particular, it's not possible to pass two float[4] uniforms to these instructions.

It appears that writing twice to the same output register can cause problems (e.g. GPU hangs).

DST mapping :

{| class="wikitable" border="1"
|-
! DST raw value
! Register name
! Description
|-
| 0x0-0x6
| o0-o6
| Output registers.
|-
| 0x10-0x1F
| r0-r15
| Temporary registers.
|}

SRC mapping :

{| class="wikitable" border="1"
|-
! SRC1 raw value
! Register name
! Description
|-
| 0x0-0x7
| v0-v7
| Input attribute registers.
|-
| 0x10-0x1F
| r0-r15
| Temporary registers.
|-
| 0x20-0x7F
| c0-c95
| Vector uniform registers.
|}

== Floating-Point Behavior ==

The PICA200 is not IEEE-compliant. It has positive and negative infinities and NaN, but does not seem to have negative 0. Several instructions also have behavior that differs from the IEEE functions. Here are the results from some tests done on hardware:

{| class="wikitable" border="1"
|-
! Computation
! Result
! Notes
|-
| inf * 0
| 0
| Including inside MUL, MAD, DP4, etc.
|-
| NaN * 0
| NaN
|
|-
| +inf - +inf
| NaN
| Indicates +inf is real inf, not FLT_MAX
|-
| rsq(rcp(-inf))
| +inf
| Indicates that there isn't -0.0.

|- style="border-top: double"
| rcp(0)
| +inf
|
|-
| rcp(+inf)
| 0
|
|-
| rcp(NaN)
| NaN
|

|- style="border-top: double"
| rsq(-0)
| +inf
| no -0 so differs from IEEE where rsq(-0) = -inf
|-
| rsq(-2)
| NaN
|
|-
| rsq(+inf)
| 0
|
|-
| rsq(-inf)
| NaN
|
|-
| rsq(NaN)
| NaN
|

|- style="border-top: double"
| max(0, +inf)
| +inf
|
|-
| max(0, -inf)
| -inf
|
|-
| max(0, NaN)
| NaN
| max violates IEEE but match GLSL spec
|-
| max(NaN, 0)
| 0
|
|-
| max(-inf, +inf)
| +inf
|

|- style="border-top: double"
| min(0, +inf)
| 0
|
|-
| min(0, -inf)
| -inf
|
|-
| min(0, NaN)
| NaN
| min violates IEEE but match GLSL spec
|-
| min(NaN, 0)
| 0
|
|-
| min(-inf, +inf)
| -inf
|
|}

GPU/Internal Registers

2015-12-07T00:45:19Z

Yuriks: /* GPUREG_FIXEDATTRIB_DATAi */ Remove stray text forgotten while editing

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-30
| Number of extra parameters (may be zero)
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X
|-
| 16-25
| unsigned, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1)
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = not perspective, 1 = perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U2
|-
| 2
| V
|-
| 3
| V2
|-
| 4
| U + V
|-
| 5
| U2 + V2
|-
| 6
| sqrt(U2*U2 + V2*V2)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-10
| 0x60
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset
|-
| 8-31
| 0xE0C080
|}

This register is used to set the procedural texture unit's offset.

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| fixed1.0.7, Red difference between current and next color table elements
|-
| 8-15
| fixed1.0.7, Green difference between current and next color table elements
|-
| 16-23
| fixed1.0.7, Blue difference between current and next color table elements
|-
| 24-31
| fixed1.0.7, Alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

Equation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|}

This register configures gas light shading in the line-of-sight direction.

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|}

This register is used to configure the gas depth direction attenuation proportion.

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20-22
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = true, 1 = false)
|-
| 1
| unsigned, Boolean register b1 value (0 = true, 1 = false)
|-
| 2
| unsigned, Boolean register b2 value (0 = true, 1 = false)
|-
| 3
| unsigned, Boolean register b3 value (0 = true, 1 = false)
|-
| 4
| unsigned, Boolean register b4 value (0 = true, 1 = false)
|-
| 5
| unsigned, Boolean register b5 value (0 = true, 1 = false)
|-
| 6
| unsigned, Boolean register b6 value (0 = true, 1 = false)
|-
| 7
| unsigned, Boolean register b7 value (0 = true, 1 = false)
|-
| 8
| unsigned, Boolean register b8 value (0 = true, 1 = false)
|-
| 9
| unsigned, Boolean register b9 value (0 = true, 1 = false)
|-
| 10
| unsigned, Boolean register b10 value (0 = true, 1 = false)
|-
| 11
| unsigned, Boolean register b11 value (0 = true, 1 = false)
|-
| 12
| unsigned, Boolean register b12 value (0 = true, 1 = false)
|-
| 13
| unsigned, Boolean register b13 value (0 = true, 1 = false)
|-
| 14
| unsigned, Boolean register b14 value (0 = true, 1 = false)
|-
| 15
| unsigned, Boolean register b15 value (0 = true, 1 = false)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

GPU/Internal Registers

2015-12-07T00:44:45Z

Yuriks: /* Geometry pipeline registers (0x200-0x27F) */ Correct index entries for FIXEDATTRIB_DATAi

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-30
| Number of extra parameters (may be zero)
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X
|-
| 16-25
| unsigned, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1)
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = not perspective, 1 = perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U2
|-
| 2
| V
|-
| 3
| V2
|-
| 4
| U + V
|-
| 5
| U2 + V2
|-
| 6
| sqrt(U2*U2 + V2*V2)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-10
| 0x60
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset
|-
| 8-31
| 0xE0C080
|}

This register is used to set the procedural texture unit's offset.

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| fixed1.0.7, Red difference between current and next color table elements
|-
| 8-15
| fixed1.0.7, Green difference between current and next color table elements
|-
| 16-23
| fixed1.0.7, Blue difference between current and next color table elements
|-
| 24-31
| fixed1.0.7, Alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

Equation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|}

This register configures gas light shading in the line-of-sight direction.

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|}

This register is used to configure the gas depth direction attenuation proportion.

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20-22
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

'''DATA0:'''
{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = true, 1 = false)
|-
| 1
| unsigned, Boolean register b1 value (0 = true, 1 = false)
|-
| 2
| unsigned, Boolean register b2 value (0 = true, 1 = false)
|-
| 3
| unsigned, Boolean register b3 value (0 = true, 1 = false)
|-
| 4
| unsigned, Boolean register b4 value (0 = true, 1 = false)
|-
| 5
| unsigned, Boolean register b5 value (0 = true, 1 = false)
|-
| 6
| unsigned, Boolean register b6 value (0 = true, 1 = false)
|-
| 7
| unsigned, Boolean register b7 value (0 = true, 1 = false)
|-
| 8
| unsigned, Boolean register b8 value (0 = true, 1 = false)
|-
| 9
| unsigned, Boolean register b9 value (0 = true, 1 = false)
|-
| 10
| unsigned, Boolean register b10 value (0 = true, 1 = false)
|-
| 11
| unsigned, Boolean register b11 value (0 = true, 1 = false)
|-
| 12
| unsigned, Boolean register b12 value (0 = true, 1 = false)
|-
| 13
| unsigned, Boolean register b13 value (0 = true, 1 = false)
|-
| 14
| unsigned, Boolean register b14 value (0 = true, 1 = false)
|-
| 15
| unsigned, Boolean register b15 value (0 = true, 1 = false)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

GPU/Internal Registers

2015-12-07T00:43:32Z

Yuriks: /* Geometry pipeline registers */ Correct documentation about the GPUREG_FIXEDATTRIB_DATAi registers

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-30
| Number of extra parameters (may be zero)
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA0|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA1|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA2|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X
|-
| 16-25
| unsigned, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1)
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = not perspective, 1 = perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U2
|-
| 2
| V
|-
| 3
| V2
|-
| 4
| U + V
|-
| 5
| U2 + V2
|-
| 6
| sqrt(U2*U2 + V2*V2)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-10
| 0x60
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset
|-
| 8-31
| 0xE0C080
|}

This register is used to set the procedural texture unit's offset.

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed1.0.11, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| fixed1.0.7, Red difference between current and next color table elements
|-
| 8-15
| fixed1.0.7, Green difference between current and next color table elements
|-
| 16-23
| fixed1.0.7, Blue difference between current and next color table elements
|-
| 24-31
| fixed1.0.7, Alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

Equation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|}

This register configures gas light shading in the line-of-sight direction.

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|}

This register is used to configure the gas depth direction attenuation proportion.

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20-22
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

'''DATA0:'''
{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = true, 1 = false)
|-
| 1
| unsigned, Boolean register b1 value (0 = true, 1 = false)
|-
| 2
| unsigned, Boolean register b2 value (0 = true, 1 = false)
|-
| 3
| unsigned, Boolean register b3 value (0 = true, 1 = false)
|-
| 4
| unsigned, Boolean register b4 value (0 = true, 1 = false)
|-
| 5
| unsigned, Boolean register b5 value (0 = true, 1 = false)
|-
| 6
| unsigned, Boolean register b6 value (0 = true, 1 = false)
|-
| 7
| unsigned, Boolean register b7 value (0 = true, 1 = false)
|-
| 8
| unsigned, Boolean register b8 value (0 = true, 1 = false)
|-
| 9
| unsigned, Boolean register b9 value (0 = true, 1 = false)
|-
| 10
| unsigned, Boolean register b10 value (0 = true, 1 = false)
|-
| 11
| unsigned, Boolean register b11 value (0 = true, 1 = false)
|-
| 12
| unsigned, Boolean register b12 value (0 = true, 1 = false)
|-
| 13
| unsigned, Boolean register b13 value (0 = true, 1 = false)
|-
| 14
| unsigned, Boolean register b14 value (0 = true, 1 = false)
|-
| 15
| unsigned, Boolean register b15 value (0 = true, 1 = false)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

KHeapChunkHeader

2015-09-27T18:37:15Z

Yuriks:

This is the header stored at the beginning of unused blocks of FCRAM memory. The kernel maintains these structures to keep a list of free blocks and their sizes.

By overwriting the pointers in instances of this struct (e.g. using an attack like gspwn) and then (de)allocating memory, one can achieve a controlled ARM11 kernel-mode write on system versions up to 9.2 ([[3DS_System_Flaws#Kernel11|memchunkhax]]).

Size : 0xC bytes?

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| u32
| Size in pages
|-
| 0x4
| KHeapHeader*
| Next
|-
| 0x8
| KHeapHeader*
| Prev
|}

GPU/Internal Registers

2015-09-15T00:28:15Z

Yuriks: /* GPUREG_SH_OUTMAP_Oi */ Add italics to heading

[[Category:GFX]]
(this page is hugely WIP)

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_0047|GPUREG_0047]]
|?
|PICA_REG_FRAG_OP_CLIP
|-
| 0048
| [[#GPUREG_0048|GPUREG_0048]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_0049|GPUREG_0049]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_004A|GPUREG_004A]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_004B|GPUREG_004B]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_0061|GPUREG_0061]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_0062|GPUREG_0062]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_0063|GPUREG_0063]]
|
|
|-
| 0064
| [[#GPUREG_0064|GPUREG_0064]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_006A|GPUREG_006A]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_006D|GPUREG_006D]]
|?
|PICA_REG_FRAG_OP_WSCALE
|-
| 006E
| [[#GPUREG_FRAMEBUFFER_DIM2|GPUREG_FRAMEBUFFER_DIM2]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_006F|GPUREG_006F]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_ENABLE|GPUREG_TEXUNIT_ENABLE]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNIT0_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNIT0_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNIT0_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_0084|GPUREG_0084]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNIT0_LOC|GPUREG_TEXUNIT0_LOC]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_0086|GPUREG_0086]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_0087|GPUREG_0087]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_0088|GPUREG_0088]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_0089|GPUREG_0089]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_008A|GPUREG_008A]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_008B|GPUREG_008B]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNIT0_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNIT1_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNIT1_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNIT1_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_0094|GPUREG_0094]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNIT1_LOC|GPUREG_TEXUNIT1_LOC]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNIT1_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNIT2_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNIT2_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNIT2_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_009C|GPUREG_009C]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNIT2_LOC|GPUREG_TEXUNIT2_LOC]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNIT2_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_00A8|GPUREG_00A8]]
|?
|PICA_REG_TEXTURE3_PROTEX0
|-
| 00A9
| [[#GPUREG_00A9|GPUREG_00A9]]
|?
|PICA_REG_TEXTURE3_PROTEX1
|-
| 00AA
| [[#GPUREG_00AA|GPUREG_00AA]]
|?
|PICA_REG_TEXTURE3_PROTEX2
|-
| 00AB
| [[#GPUREG_00AB|GPUREG_00AB]]
|?
|PICA_REG_TEXTURE3_PROTEX3
|-
| 00AC
| [[#GPUREG_00AC|GPUREG_00AC]]
|?
|PICA_REG_TEXTURE3_PROTEX4
|-
| 00AD
| [[#GPUREG_00AD|GPUREG_00AD]]
|?
|PICA_REG_TEXTURE3_PROTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_00AF|GPUREG_00AF]]
|?
|PICA_REG_PROTEX_LUT
|-
| 00B0
| [[#GPUREG_00B0|GPUREG_00B0]]
| ?
|PICA_REG_PROTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_00B1|GPUREG_00B1]]
| ?
|PICA_REG_PROTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_00B2|GPUREG_00B2]]
| ?
|PICA_REG_PROTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_00B3|GPUREG_00B3]]
| ?
|PICA_REG_PROTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_00B4|GPUREG_00B4]]
| ?
|PICA_REG_PROTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_00B5|GPUREG_00B5]]
| ?
|PICA_REG_PROTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_00B6|GPUREG_00B6]]
| ?
|PICA_REG_PROTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_00B7|GPUREG_00B7]]
| ?
|PICA_REG_PROTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENV0_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENV0_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENV0_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENV0_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENV0_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENV1_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENV1_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENV1_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENV1_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENV1_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENV2_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENV2_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENV2_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENV2_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENV2_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENV3_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENV3_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENV3_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENV3_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENV3_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_00E1|GPUREG_00E1]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_00E4|GPUREG_00E4]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_00E5|GPUREG_00E5]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_00E6|GPUREG_00E6]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_00E8|GPUREG_00E8]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_00E9|GPUREG_00E9]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_00EA|GPUREG_00EA]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_00EB|GPUREG_00EB]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_00EC|GPUREG_00EC]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_00ED|GPUREG_00ED]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_00EE|GPUREG_00EE]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_00EF|GPUREG_00EF]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENV4_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENV4_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENV4_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENV4_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENV4_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENV5_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENV5_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENV5_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENV5_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENV5_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_BLEND_ENABLE|GPUREG_BLEND_ENABLE]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_CONFIG|GPUREG_BLEND_CONFIG]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGICOP_CONFIG|GPUREG_LOGICOP_CONFIG]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_ALPHATEST_CONFIG|GPUREG_ALPHATEST_CONFIG]]
|
|PICA_REG_FRAG_OP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_ACTION|GPUREG_STENCIL_ACTION]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTHTEST_CONFIG|GPUREG_DEPTHTEST_CONFIG]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_0118|GPUREG_0118]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_0120|GPUREG_0120]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_0121|GPUREG_0121]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_0122|GPUREG_0122]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_0123|GPUREG_0123]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_0124|GPUREG_0124]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_0126|GPUREG_0126]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_0130|GPUREG_0130]]
|?
|PICA_REG_FRAG_OP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|
|-
| 019B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|
|-
| 01AB
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|
|-
| 01BB
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFER0_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFER0_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFER0_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFER1_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFER1_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFER1_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFER2_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFER2_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFER2_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFER3_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFER3_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFER3_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFER4_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFER4_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFER4_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFER5_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFER5_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFER5_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFER6_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFER6_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFER6_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFER7_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFER7_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFER7_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFER8_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFER8_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFER8_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFER9_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFER9_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFER9_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFER10_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFER10_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFER10_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFER11_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFER11_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFER11_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_022D|GPUREG_022D]]
|
|
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_0231|GPUREG_0231]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_0242|GPUREG_0242]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_0244|GPUREG_0244]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_0245|GPUREG_0245]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_024A|GPUREG_024A]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_0251|GPUREG_0251]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_0252|GPUREG_0252]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_0253|GPUREG_0253]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_0254|GPUREG_0254]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_GSH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_GSH_INTUNIFORM_I0|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_GSH_INTUNIFORM_I1|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_GSH_INTUNIFORM_I2|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_GSH_INTUNIFORM_I3|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_GSH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_GSH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_GSH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0292
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0293
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0294
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0295
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0296
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0297
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0298
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA8
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_GSH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_GSH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_VSH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_VSH_INTUNIFORM_I0|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_VSH_INTUNIFORM_I1|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_VSH_INTUNIFORM_I2|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_VSH_INTUNIFORM_I3|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_VSH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_VSH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C2
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C3
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C4
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C5
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C6
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C7
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C8
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA8
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_VSH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_VSH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_SH_OUTMAP_O''i'' ===

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Semantic for the x component of the register.
|-
| 8-15
| Semantic for the y component of the register.
|-
| 16-23
| Semantic for the z component of the register.
|-
| 24-31
| Semantic for the w component of the register.
|}

The semantic ids are:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

== Texturing registers ==

== Framebuffer registers ==

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_DEPTHBUFFER_FORMAT ===

The format the current depth buffer should be written into. Following values are possible:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 1
| ?? seems to freeze the GPU
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil (stencil is within bit 24-31)
|}

=== GPUREG_COLORBUFFER_FORMAT ===

Describes the format of the current color buffer used for 3D rendering.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?)
|-
| 16-23
| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].

Color components are laid out in reverse byte order, with the most significant bits used first.
|}

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

When set to 0, use regular 8x8 tiling format for the framebuffer, compatible with textures. When set to 1, use a 32x32 tiling format. To untile the color buffer when using this format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

== Fragment lighting registers ==

=== GPUREG_LIGHTING_ENABLE0 ===

This register is set to 0 when fragment lighting is disabled, and to 1 when it is enabled.

=== GPUREG_LIGHTING_ENABLE1 ===

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Shadow factor enable, usually set to bit16 OR bit18 OR bit19
|-
| 1
| Unknown, set to 0
|-
| 2-3
| "Fresnel selector" (see below)
|-
| 4-7
| "Config", "Light env config" (see below)
|-
| 8-15
| Unknown, set to 4
|-
| 16
| "Shadow primary", 0=disabled, 1=enabled
|-
| 17
| "Shadow secondary", 0=disabled, 1=enabled
|-
| 18
| "Invert shadow", 0=disabled, 1=enabled
|-
| 19
| "Shadow alpha", 0=disabled, 1=enabled
|-
| 20-21
| Unknown, set to 0
|-
| 22-23
| "Bump selector"
|-
| 24-25
| "Shadow selector"
|-
| 26
| Unknown, set to 0
|-
| 27
| "Clamp highlights", 0=disabled, 1=enabled
|-
| 28-29
| "Bump mode", "Light env texy usage" (see below)
|-
| 30
| "Bump renorm", 0=enabled, 1=disabled
|-
| 31
| Unknown, set to 1
|}

Fresnel selector constants:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| NO_FRESNEL
|-
| 1
| PRI_ALPHA_FRESNEL
|-
| 2
| SEC_ALPHA_FRESNEL
|-
| 3
| PRI_SEC_ALPHA_FRESNEL
|}

Light env config constants:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| LIGHT_ENV_LAYER_CONFIG0
|-
| 1
| LIGHT_ENV_LAYER_CONFIG1
|-
| 2
| LIGHT_ENV_LAYER_CONFIG2
|-
| 3
| LIGHT_ENV_LAYER_CONFIG3
|-
| 4
| LIGHT_ENV_LAYER_CONFIG4
|-
| 5
| LIGHT_ENV_LAYER_CONFIG5
|-
| 6
| LIGHT_ENV_LAYER_CONFIG6
|-
| 8 (sic)
| LIGHT_ENV_LAYER_CONFIG7
|}

Bump mode constants:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| BUMP_NOT_USED
|-
| 1
| BUMP_AS_BUMP
|-
| 2
| BUMP_AS_TANG
|}

Bit 30 is set when bump mode is not zero.

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Disable bit for frag light source 0 shadows
|-
| 1
| Disable bit for frag light source 1 shadows
|-
| 2
| Disable bit for frag light source 2 shadows
|-
| 3
| Disable bit for frag light source 3 shadows
|-
| 4
| Disable bit for frag light source 4 shadows
|-
| 5
| Disable bit for frag light source 5 shadows
|-
| 6
| Disable bit for frag light source 6 shadows
|-
| 7
| Disable bit for frag light source 7 shadows
|-
| 8
| Disable bit for frag light source 0 spot
|-
| 9
| Disable bit for frag light source 1 spot
|-
| 10
| Disable bit for frag light source 2 spot
|-
| 11
| Disable bit for frag light source 3 spot
|-
| 12
| Disable bit for frag light source 4 spot
|-
| 13
| Disable bit for frag light source 5 spot
|-
| 14
| Disable bit for frag light source 6 spot
|-
| 15
| Disable bit for frag light source 7 spot
|-
| 16
| Disable bit for lut_D0
|-
| 17
| Disable bit for lut_D1
|-
| 18
| Unknown, set to 1
|-
| 19
| Disable bit for lut_FR
|-
| 20
| Disable bit for lut_RB
|-
| 21
| Disable bit for lut_RG
|-
| 22
| Disable bit for lut_RR
|-
| 23
| Unknown, set to 1
|-
| 24
| Disable bit for frag light source 0 distance attenuation
|-
| 25
| Disable bit for frag light source 1 distance attenuation
|-
| 26
| Disable bit for frag light source 2 distance attenuation
|-
| 27
| Disable bit for frag light source 3 distance attenuation
|-
| 28
| Disable bit for frag light source 4 distance attenuation
|-
| 29
| Disable bit for frag light source 5 distance attenuation
|-
| 30
| Disable bit for frag light source 6 distance attenuation
|-
| 31
| Disable bit for frag light source 7 distance attenuation
|}

=== GPUREG_LIGHTING_NUM_LIGHTS ===

The number of active lights minus one (0..7) is written to this register.

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| ID of the 1st enabled light (0..7)
|-
| 4-6
| ID of the 2nd enabled light (0..7)
|-
| 8-10
| ID of the 3rd enabled light (0..7)
|-
| 12-14
| ID of the 4th enabled light (0..7)
|-
| 16-18
| ID of the 5th enabled light (0..7)
|-
| 20-22
| ID of the 6th enabled light (0..7)
|-
| 24-26
| ID of the 7th enabled light (0..7)
|-
| 28-30
| ID of the 8th enabled light (0..7)
|}

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Input selector for lut_D0
|-
| 4-7
| Input selector for lut_D1
|-
| 8-11
| Input selector for lut_SP
|-
| 12-15
| Input selector for lut_FR
|-
| 16-19
| Input selector for lut_RB
|-
| 20-23
| Input selector for lut_RG
|-
| 24-27
| Input selector for lut_RR
|-
| 28-31
| Input selector for lut_DA
|}

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| abs() flag for the input of lut_D0 (0=enabled, 1=disabled)
|-
| 5
| abs() flag for the input of lut_D1 (0=enabled, 1=disabled)
|-
| 9
| abs() flag for the input of lut_SP (0=enabled, 1=disabled)
|-
| 13
| abs() flag for the input of lut_FR (0=enabled, 1=disabled)
|-
| 17
| abs() flag for the input of lut_RB (0=enabled, 1=disabled)
|-
| 21
| abs() flag for the input of lut_RG (0=enabled, 1=disabled)
|-
| 25
| abs() flag for the input of lut_RR (0=enabled, 1=disabled)
|-
| 29
| abs() flag for the input of lut_DA (0=enabled, 1=disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Scaler selector for lut_D0
|-
| 4-7
| Scaler selector for lut_D1
|-
| 8-11
| Scaler selector for lut_SP
|-
| 12-15
| Scaler selector for lut_FR
|-
| 16-19
| Scaler selector for lut_RB
|-
| 20-23
| Scaler selector for lut_RG
|-
| 24-27
| Scaler selector for lut_RR
|-
| 28-31
| Scaler selector for lut_DA
|}

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

This register controls the scaling that is applied to the output of a LUT.

=== GPUREG_LIGHTING_LUT_INDEX ===

This register controls which LUT and what offset into it the LUT_DATA register writes to.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Starting entry offset (0...255)
|-
| 8-10
| LUT ID (context=0) or Light ID (context=1,2)
|-
| 11-12
| Context ID
|}

LUT ID values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| lut_D0
|-
| 1
| lut_D1
|-
| 3
| lut_FR
|-
| 4
| lut_RB
|-
| 5
| lut_RG
|-
| 6
| lut_RR
|}

Context ID values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| LUTs common to all lights - writes to the LUT selected by the ID
|-
| 1
| lut_SP - writes to the LUT specific to the selected light
|-
| 2
| lut_DA - writes to the LUT specific to the selected light
|}

=== GPUREG_LIGHTING_LUT_DATA ===

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Entry value (12bit fractional number; floatval = x / 4096; however 0xFFF is treated as 1.0)
|-
| 12-22
| Absolute value of the difference between the next entry and this entry (11bit fractional number; floatval = x / 2048; however 0x7FF is treated as 1.0)
|-
| 23
| Sign bit of the difference (0=positive, 1=negative)
|}

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Blue component (0..255)
|-
| 10-17
| Green component (0..255)
|-
| 20-27
| Red component (0..255)
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTx_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Light type (0 = positional light, 1 = directional light)
|-
| 1
| Two side diffuse (0=disable, 1=enable)
|-
| 2
| Geometric factor 0 (0=disable, 1=enable)
|-
| 3
| Geometric factor 1 (0=disable, 1=enable)
|}

=== GPUREG_LIGHTx_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| X coordinate (float16 = 1.5.10)
|-
| 16-31
| Y coordinate (float16 = 1.5.10)
|}

These registers (along with _Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHTx_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Z coordinate (float16 = 1.5.10)
|}

These registers (along with _XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHTx_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| X coordinate (2.11 signed fixed point) (Usually the input value is negated)
|-
| 16-28
| Y coordinate (2.11 signed fixed point) (Usually the input value is negated)
|}

These registers (along with _Z) represent the spot direction (unitary) vector of the corresponding light .

=== GPUREG_LIGHTx_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| Z coordinate (2.11 signed fixed point) (Usually the input value is negated)
|}

These registers (along with _XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHTx_ATTENUATION_BIAS ===

These registers contain the distance attenuation bias value (float20 = 1.7.12) of the corresponding light.

=== GPUREG_LIGHTx_ATTENUATION_SCALE ===

These registers contain the distance attenuation scale value (float20 = 1.7.12) of the corresponding light.

=== GPUREG_LIGHTx_AMBIENT ===

These registers contain the ambient color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHTx_DIFFUSE ===

These registers contain the diffuse color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHTx_SPECULAR0 ===

These registers contain the specular0 color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHTx_SPECULAR1 ===

These registers contain the specular1 color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_specular1*lightX_specular1.

== Geometry pipeline registers ==

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
|-
| 8
| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''
|-
| 9-15
| No effect.
|-
| 16-23
| Unknown.
|-
| 24-31
| Unknown. Often set to 0.
|}

This register configures the geometry stage of the GPU pipeline.

=== GPUREG_FIXEDATTRIB_INDEX ===

See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline.
|}

=== GPUREG_FIXEDATTRIB_DATA ===

Accepts a packed 4-tuple of float24 values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].

If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]], but most games seem to write to it before every draw call.
|}

== Geometry shader registers ==

=== GPUREG_GSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the geometry shader unit's boolean registers.

=== GPUREG_GSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i0.w (u8, 0-255)
|}

This register is used to set the geometry shader's i0 integer register.

=== GPUREG_GSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i1.w (u8, 0-255)
|}

This register is used to set the geometry shader's i1 integer register.

=== GPUREG_GSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i2.w (u8, 0-255)
|}

This register is used to set the geometry shader's i2 integer register.

=== GPUREG_GSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i3.w (u8, 0-255)
|}

This register is used to set the geometry shader's i3 integer register.

=== GPUREG_GSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 8 for geometry shaders.
|}

This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.

=== GPUREG_GSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Geometry shader unit entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 8th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 16th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_GSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|}

This register toggles the geometry shader unit's output registers.

=== GPUREG_GSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.

=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_GSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_GSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target geometry shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_GSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader instruction data.
|}

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_GSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target geometry shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.

=== GPUREG_GSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader operand descriptor data.
|}

This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

== Vertex shader registers ==

=== GPUREG_VSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of vertex shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of vertex shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of vertex shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of vertex shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of vertex shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of vertex shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of vertex shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of vertex shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the vertex shader unit's boolean registers.

=== GPUREG_VSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i0.w (u8, 0-255)
|}

This register is used to set the vertex shader's i0 integer register.

=== GPUREG_VSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i1.w (u8, 0-255)
|}

This register is used to set the vertex shader's i1 integer register.

=== GPUREG_VSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i2.w (u8, 0-255)
|}

This register is used to set the vertex shader's i2 integer register.

=== GPUREG_VSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i3.w (u8, 0-255)
|}

This register is used to set the vertex shader's i3 integer register.

=== GPUREG_VSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 0xA for vertex shaders.
|}

This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.

=== GPUREG_VSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Vertex shader entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 8th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 16th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_VSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|-
| 7
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
|-
| 8
| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
|-
| 9
| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
|-
| 10
| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
|-
| 11
| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
|-
| 12
| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
|-
| 13
| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
|-
| 14
| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
|-
| 15
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
|}

This register toggles the vertex shader units' output registers.

=== GPUREG_VSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.

=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_VSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_VSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target vertex shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_VSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader instruction data.
|}

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_VSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target vertex shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.

=== GPUREG_VSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader operand descriptor data.
|}

This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

[[Category:GPU]]

GPU/Internal Registers

2015-09-15T00:27:07Z

Yuriks: /* Rasterizer registers */ Documented GPUREG_SH_OUTMAP_Oi

[[Category:GFX]]
(this page is hugely WIP)

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_0047|GPUREG_0047]]
|?
|PICA_REG_FRAG_OP_CLIP
|-
| 0048
| [[#GPUREG_0048|GPUREG_0048]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_0049|GPUREG_0049]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_004A|GPUREG_004A]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_004B|GPUREG_004B]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_0061|GPUREG_0061]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_0062|GPUREG_0062]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_0063|GPUREG_0063]]
|
|
|-
| 0064
| [[#GPUREG_0064|GPUREG_0064]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_006A|GPUREG_006A]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_006D|GPUREG_006D]]
|?
|PICA_REG_FRAG_OP_WSCALE
|-
| 006E
| [[#GPUREG_FRAMEBUFFER_DIM2|GPUREG_FRAMEBUFFER_DIM2]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_006F|GPUREG_006F]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_ENABLE|GPUREG_TEXUNIT_ENABLE]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNIT0_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNIT0_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNIT0_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_0084|GPUREG_0084]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNIT0_LOC|GPUREG_TEXUNIT0_LOC]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_0086|GPUREG_0086]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_0087|GPUREG_0087]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_0088|GPUREG_0088]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_0089|GPUREG_0089]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_008A|GPUREG_008A]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_008B|GPUREG_008B]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNIT0_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNIT1_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNIT1_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNIT1_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_0094|GPUREG_0094]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNIT1_LOC|GPUREG_TEXUNIT1_LOC]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNIT1_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNIT2_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNIT2_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNIT2_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_009C|GPUREG_009C]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNIT2_LOC|GPUREG_TEXUNIT2_LOC]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNIT2_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_00A8|GPUREG_00A8]]
|?
|PICA_REG_TEXTURE3_PROTEX0
|-
| 00A9
| [[#GPUREG_00A9|GPUREG_00A9]]
|?
|PICA_REG_TEXTURE3_PROTEX1
|-
| 00AA
| [[#GPUREG_00AA|GPUREG_00AA]]
|?
|PICA_REG_TEXTURE3_PROTEX2
|-
| 00AB
| [[#GPUREG_00AB|GPUREG_00AB]]
|?
|PICA_REG_TEXTURE3_PROTEX3
|-
| 00AC
| [[#GPUREG_00AC|GPUREG_00AC]]
|?
|PICA_REG_TEXTURE3_PROTEX4
|-
| 00AD
| [[#GPUREG_00AD|GPUREG_00AD]]
|?
|PICA_REG_TEXTURE3_PROTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_00AF|GPUREG_00AF]]
|?
|PICA_REG_PROTEX_LUT
|-
| 00B0
| [[#GPUREG_00B0|GPUREG_00B0]]
| ?
|PICA_REG_PROTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_00B1|GPUREG_00B1]]
| ?
|PICA_REG_PROTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_00B2|GPUREG_00B2]]
| ?
|PICA_REG_PROTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_00B3|GPUREG_00B3]]
| ?
|PICA_REG_PROTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_00B4|GPUREG_00B4]]
| ?
|PICA_REG_PROTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_00B5|GPUREG_00B5]]
| ?
|PICA_REG_PROTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_00B6|GPUREG_00B6]]
| ?
|PICA_REG_PROTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_00B7|GPUREG_00B7]]
| ?
|PICA_REG_PROTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENV0_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENV0_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENV0_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENV0_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENV0_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENV1_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENV1_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENV1_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENV1_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENV1_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENV2_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENV2_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENV2_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENV2_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENV2_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENV3_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENV3_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENV3_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENV3_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENV3_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_00E1|GPUREG_00E1]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_00E4|GPUREG_00E4]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_00E5|GPUREG_00E5]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_00E6|GPUREG_00E6]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_00E8|GPUREG_00E8]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_00E9|GPUREG_00E9]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_00EA|GPUREG_00EA]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_00EB|GPUREG_00EB]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_00EC|GPUREG_00EC]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_00ED|GPUREG_00ED]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_00EE|GPUREG_00EE]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_00EF|GPUREG_00EF]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENV4_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENV4_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENV4_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENV4_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENV4_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENV5_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENV5_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENV5_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENV5_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENV5_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_BLEND_ENABLE|GPUREG_BLEND_ENABLE]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_CONFIG|GPUREG_BLEND_CONFIG]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGICOP_CONFIG|GPUREG_LOGICOP_CONFIG]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_ALPHATEST_CONFIG|GPUREG_ALPHATEST_CONFIG]]
|
|PICA_REG_FRAG_OP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_ACTION|GPUREG_STENCIL_ACTION]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTHTEST_CONFIG|GPUREG_DEPTHTEST_CONFIG]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_0118|GPUREG_0118]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_0120|GPUREG_0120]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_0121|GPUREG_0121]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_0122|GPUREG_0122]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_0123|GPUREG_0123]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_0124|GPUREG_0124]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_0126|GPUREG_0126]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_0130|GPUREG_0130]]
|?
|PICA_REG_FRAG_OP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|
|-
| 019B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|
|-
| 01AB
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|
|-
| 01BB
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFER0_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFER0_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFER0_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFER1_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFER1_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFER1_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFER2_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFER2_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFER2_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFER3_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFER3_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFER3_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFER4_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFER4_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFER4_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFER5_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFER5_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFER5_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFER6_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFER6_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFER6_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFER7_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFER7_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFER7_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFER8_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFER8_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFER8_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFER9_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFER9_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFER9_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFER10_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFER10_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFER10_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFER11_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFER11_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFER11_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_022D|GPUREG_022D]]
|
|
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_0231|GPUREG_0231]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_0242|GPUREG_0242]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_0244|GPUREG_0244]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_0245|GPUREG_0245]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_024A|GPUREG_024A]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_0251|GPUREG_0251]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_0252|GPUREG_0252]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_0253|GPUREG_0253]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_0254|GPUREG_0254]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_GSH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_GSH_INTUNIFORM_I0|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_GSH_INTUNIFORM_I1|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_GSH_INTUNIFORM_I2|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_GSH_INTUNIFORM_I3|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_GSH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_GSH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_GSH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0292
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0293
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0294
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0295
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0296
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0297
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0298
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA8
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_GSH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_GSH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_VSH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_VSH_INTUNIFORM_I0|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_VSH_INTUNIFORM_I1|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_VSH_INTUNIFORM_I2|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_VSH_INTUNIFORM_I3|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_VSH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_VSH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C2
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C3
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C4
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C5
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C6
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C7
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C8
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA8
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_VSH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_VSH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_SH_OUTMAP_Oi ===

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Semantic for the x component of the register.
|-
| 8-15
| Semantic for the y component of the register.
|-
| 16-23
| Semantic for the z component of the register.
|-
| 24-31
| Semantic for the w component of the register.
|}

The semantic ids are:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

== Texturing registers ==

== Framebuffer registers ==

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_DEPTHBUFFER_FORMAT ===

The format the current depth buffer should be written into. Following values are possible:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 1
| ?? seems to freeze the GPU
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil (stencil is within bit 24-31)
|}

=== GPUREG_COLORBUFFER_FORMAT ===

Describes the format of the current color buffer used for 3D rendering.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?)
|-
| 16-23
| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].

Color components are laid out in reverse byte order, with the most significant bits used first.
|}

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

When set to 0, use regular 8x8 tiling format for the framebuffer, compatible with textures. When set to 1, use a 32x32 tiling format. To untile the color buffer when using this format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

== Fragment lighting registers ==

=== GPUREG_LIGHTING_ENABLE0 ===

This register is set to 0 when fragment lighting is disabled, and to 1 when it is enabled.

=== GPUREG_LIGHTING_ENABLE1 ===

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Shadow factor enable, usually set to bit16 OR bit18 OR bit19
|-
| 1
| Unknown, set to 0
|-
| 2-3
| "Fresnel selector" (see below)
|-
| 4-7
| "Config", "Light env config" (see below)
|-
| 8-15
| Unknown, set to 4
|-
| 16
| "Shadow primary", 0=disabled, 1=enabled
|-
| 17
| "Shadow secondary", 0=disabled, 1=enabled
|-
| 18
| "Invert shadow", 0=disabled, 1=enabled
|-
| 19
| "Shadow alpha", 0=disabled, 1=enabled
|-
| 20-21
| Unknown, set to 0
|-
| 22-23
| "Bump selector"
|-
| 24-25
| "Shadow selector"
|-
| 26
| Unknown, set to 0
|-
| 27
| "Clamp highlights", 0=disabled, 1=enabled
|-
| 28-29
| "Bump mode", "Light env texy usage" (see below)
|-
| 30
| "Bump renorm", 0=enabled, 1=disabled
|-
| 31
| Unknown, set to 1
|}

Fresnel selector constants:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| NO_FRESNEL
|-
| 1
| PRI_ALPHA_FRESNEL
|-
| 2
| SEC_ALPHA_FRESNEL
|-
| 3
| PRI_SEC_ALPHA_FRESNEL
|}

Light env config constants:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| LIGHT_ENV_LAYER_CONFIG0
|-
| 1
| LIGHT_ENV_LAYER_CONFIG1
|-
| 2
| LIGHT_ENV_LAYER_CONFIG2
|-
| 3
| LIGHT_ENV_LAYER_CONFIG3
|-
| 4
| LIGHT_ENV_LAYER_CONFIG4
|-
| 5
| LIGHT_ENV_LAYER_CONFIG5
|-
| 6
| LIGHT_ENV_LAYER_CONFIG6
|-
| 8 (sic)
| LIGHT_ENV_LAYER_CONFIG7
|}

Bump mode constants:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| BUMP_NOT_USED
|-
| 1
| BUMP_AS_BUMP
|-
| 2
| BUMP_AS_TANG
|}

Bit 30 is set when bump mode is not zero.

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Disable bit for frag light source 0 shadows
|-
| 1
| Disable bit for frag light source 1 shadows
|-
| 2
| Disable bit for frag light source 2 shadows
|-
| 3
| Disable bit for frag light source 3 shadows
|-
| 4
| Disable bit for frag light source 4 shadows
|-
| 5
| Disable bit for frag light source 5 shadows
|-
| 6
| Disable bit for frag light source 6 shadows
|-
| 7
| Disable bit for frag light source 7 shadows
|-
| 8
| Disable bit for frag light source 0 spot
|-
| 9
| Disable bit for frag light source 1 spot
|-
| 10
| Disable bit for frag light source 2 spot
|-
| 11
| Disable bit for frag light source 3 spot
|-
| 12
| Disable bit for frag light source 4 spot
|-
| 13
| Disable bit for frag light source 5 spot
|-
| 14
| Disable bit for frag light source 6 spot
|-
| 15
| Disable bit for frag light source 7 spot
|-
| 16
| Disable bit for lut_D0
|-
| 17
| Disable bit for lut_D1
|-
| 18
| Unknown, set to 1
|-
| 19
| Disable bit for lut_FR
|-
| 20
| Disable bit for lut_RB
|-
| 21
| Disable bit for lut_RG
|-
| 22
| Disable bit for lut_RR
|-
| 23
| Unknown, set to 1
|-
| 24
| Disable bit for frag light source 0 distance attenuation
|-
| 25
| Disable bit for frag light source 1 distance attenuation
|-
| 26
| Disable bit for frag light source 2 distance attenuation
|-
| 27
| Disable bit for frag light source 3 distance attenuation
|-
| 28
| Disable bit for frag light source 4 distance attenuation
|-
| 29
| Disable bit for frag light source 5 distance attenuation
|-
| 30
| Disable bit for frag light source 6 distance attenuation
|-
| 31
| Disable bit for frag light source 7 distance attenuation
|}

=== GPUREG_LIGHTING_NUM_LIGHTS ===

The number of active lights minus one (0..7) is written to this register.

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| ID of the 1st enabled light (0..7)
|-
| 4-6
| ID of the 2nd enabled light (0..7)
|-
| 8-10
| ID of the 3rd enabled light (0..7)
|-
| 12-14
| ID of the 4th enabled light (0..7)
|-
| 16-18
| ID of the 5th enabled light (0..7)
|-
| 20-22
| ID of the 6th enabled light (0..7)
|-
| 24-26
| ID of the 7th enabled light (0..7)
|-
| 28-30
| ID of the 8th enabled light (0..7)
|}

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Input selector for lut_D0
|-
| 4-7
| Input selector for lut_D1
|-
| 8-11
| Input selector for lut_SP
|-
| 12-15
| Input selector for lut_FR
|-
| 16-19
| Input selector for lut_RB
|-
| 20-23
| Input selector for lut_RG
|-
| 24-27
| Input selector for lut_RR
|-
| 28-31
| Input selector for lut_DA
|}

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| abs() flag for the input of lut_D0 (0=enabled, 1=disabled)
|-
| 5
| abs() flag for the input of lut_D1 (0=enabled, 1=disabled)
|-
| 9
| abs() flag for the input of lut_SP (0=enabled, 1=disabled)
|-
| 13
| abs() flag for the input of lut_FR (0=enabled, 1=disabled)
|-
| 17
| abs() flag for the input of lut_RB (0=enabled, 1=disabled)
|-
| 21
| abs() flag for the input of lut_RG (0=enabled, 1=disabled)
|-
| 25
| abs() flag for the input of lut_RR (0=enabled, 1=disabled)
|-
| 29
| abs() flag for the input of lut_DA (0=enabled, 1=disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Scaler selector for lut_D0
|-
| 4-7
| Scaler selector for lut_D1
|-
| 8-11
| Scaler selector for lut_SP
|-
| 12-15
| Scaler selector for lut_FR
|-
| 16-19
| Scaler selector for lut_RB
|-
| 20-23
| Scaler selector for lut_RG
|-
| 24-27
| Scaler selector for lut_RR
|-
| 28-31
| Scaler selector for lut_DA
|}

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

This register controls the scaling that is applied to the output of a LUT.

=== GPUREG_LIGHTING_LUT_INDEX ===

This register controls which LUT and what offset into it the LUT_DATA register writes to.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Starting entry offset (0...255)
|-
| 8-10
| LUT ID (context=0) or Light ID (context=1,2)
|-
| 11-12
| Context ID
|}

LUT ID values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| lut_D0
|-
| 1
| lut_D1
|-
| 3
| lut_FR
|-
| 4
| lut_RB
|-
| 5
| lut_RG
|-
| 6
| lut_RR
|}

Context ID values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| LUTs common to all lights - writes to the LUT selected by the ID
|-
| 1
| lut_SP - writes to the LUT specific to the selected light
|-
| 2
| lut_DA - writes to the LUT specific to the selected light
|}

=== GPUREG_LIGHTING_LUT_DATA ===

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Entry value (12bit fractional number; floatval = x / 4096; however 0xFFF is treated as 1.0)
|-
| 12-22
| Absolute value of the difference between the next entry and this entry (11bit fractional number; floatval = x / 2048; however 0x7FF is treated as 1.0)
|-
| 23
| Sign bit of the difference (0=positive, 1=negative)
|}

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Blue component (0..255)
|-
| 10-17
| Green component (0..255)
|-
| 20-27
| Red component (0..255)
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTx_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Light type (0 = positional light, 1 = directional light)
|-
| 1
| Two side diffuse (0=disable, 1=enable)
|-
| 2
| Geometric factor 0 (0=disable, 1=enable)
|-
| 3
| Geometric factor 1 (0=disable, 1=enable)
|}

=== GPUREG_LIGHTx_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| X coordinate (float16 = 1.5.10)
|-
| 16-31
| Y coordinate (float16 = 1.5.10)
|}

These registers (along with _Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHTx_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Z coordinate (float16 = 1.5.10)
|}

These registers (along with _XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHTx_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| X coordinate (2.11 signed fixed point) (Usually the input value is negated)
|-
| 16-28
| Y coordinate (2.11 signed fixed point) (Usually the input value is negated)
|}

These registers (along with _Z) represent the spot direction (unitary) vector of the corresponding light .

=== GPUREG_LIGHTx_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| Z coordinate (2.11 signed fixed point) (Usually the input value is negated)
|}

These registers (along with _XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHTx_ATTENUATION_BIAS ===

These registers contain the distance attenuation bias value (float20 = 1.7.12) of the corresponding light.

=== GPUREG_LIGHTx_ATTENUATION_SCALE ===

These registers contain the distance attenuation scale value (float20 = 1.7.12) of the corresponding light.

=== GPUREG_LIGHTx_AMBIENT ===

These registers contain the ambient color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHTx_DIFFUSE ===

These registers contain the diffuse color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHTx_SPECULAR0 ===

These registers contain the specular0 color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHTx_SPECULAR1 ===

These registers contain the specular1 color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_specular1*lightX_specular1.

== Geometry pipeline registers ==

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
|-
| 8
| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''
|-
| 9-15
| No effect.
|-
| 16-23
| Unknown.
|-
| 24-31
| Unknown. Often set to 0.
|}

This register configures the geometry stage of the GPU pipeline.

=== GPUREG_FIXEDATTRIB_INDEX ===

See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline.
|}

=== GPUREG_FIXEDATTRIB_DATA ===

Accepts a packed 4-tuple of float24 values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].

If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]], but most games seem to write to it before every draw call.
|}

== Geometry shader registers ==

=== GPUREG_GSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the geometry shader unit's boolean registers.

=== GPUREG_GSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i0.w (u8, 0-255)
|}

This register is used to set the geometry shader's i0 integer register.

=== GPUREG_GSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i1.w (u8, 0-255)
|}

This register is used to set the geometry shader's i1 integer register.

=== GPUREG_GSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i2.w (u8, 0-255)
|}

This register is used to set the geometry shader's i2 integer register.

=== GPUREG_GSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i3.w (u8, 0-255)
|}

This register is used to set the geometry shader's i3 integer register.

=== GPUREG_GSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 8 for geometry shaders.
|}

This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.

=== GPUREG_GSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Geometry shader unit entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 8th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 16th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_GSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|}

This register toggles the geometry shader unit's output registers.

=== GPUREG_GSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.

=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_GSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_GSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target geometry shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_GSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader instruction data.
|}

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_GSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target geometry shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.

=== GPUREG_GSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader operand descriptor data.
|}

This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

== Vertex shader registers ==

=== GPUREG_VSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of vertex shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of vertex shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of vertex shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of vertex shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of vertex shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of vertex shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of vertex shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of vertex shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the vertex shader unit's boolean registers.

=== GPUREG_VSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i0.w (u8, 0-255)
|}

This register is used to set the vertex shader's i0 integer register.

=== GPUREG_VSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i1.w (u8, 0-255)
|}

This register is used to set the vertex shader's i1 integer register.

=== GPUREG_VSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i2.w (u8, 0-255)
|}

This register is used to set the vertex shader's i2 integer register.

=== GPUREG_VSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i3.w (u8, 0-255)
|}

This register is used to set the vertex shader's i3 integer register.

=== GPUREG_VSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 0xA for vertex shaders.
|}

This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.

=== GPUREG_VSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Vertex shader entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 8th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 16th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_VSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|-
| 7
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
|-
| 8
| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
|-
| 9
| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
|-
| 10
| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
|-
| 11
| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
|-
| 12
| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
|-
| 13
| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
|-
| 14
| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
|-
| 15
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
|}

This register toggles the vertex shader units' output registers.

=== GPUREG_VSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.

=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_VSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_VSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target vertex shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_VSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader instruction data.
|}

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_VSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target vertex shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.

=== GPUREG_VSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader operand descriptor data.
|}

This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

[[Category:GPU]]

GPU/Internal Registers

2015-09-15T00:06:31Z

Yuriks: /* Rasterizer registers (0x040-0x07F) */

[[Category:GFX]]
(this page is hugely WIP)

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_0047|GPUREG_0047]]
|?
|PICA_REG_FRAG_OP_CLIP
|-
| 0048
| [[#GPUREG_0048|GPUREG_0048]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_0049|GPUREG_0049]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_004A|GPUREG_004A]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_004B|GPUREG_004B]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_0061|GPUREG_0061]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_0062|GPUREG_0062]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_0063|GPUREG_0063]]
|
|
|-
| 0064
| [[#GPUREG_0064|GPUREG_0064]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_006A|GPUREG_006A]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_006D|GPUREG_006D]]
|?
|PICA_REG_FRAG_OP_WSCALE
|-
| 006E
| [[#GPUREG_FRAMEBUFFER_DIM2|GPUREG_FRAMEBUFFER_DIM2]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_006F|GPUREG_006F]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_ENABLE|GPUREG_TEXUNIT_ENABLE]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNIT0_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNIT0_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNIT0_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_0084|GPUREG_0084]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNIT0_LOC|GPUREG_TEXUNIT0_LOC]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_0086|GPUREG_0086]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_0087|GPUREG_0087]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_0088|GPUREG_0088]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_0089|GPUREG_0089]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_008A|GPUREG_008A]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_008B|GPUREG_008B]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNIT0_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNIT1_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNIT1_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNIT1_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_0094|GPUREG_0094]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNIT1_LOC|GPUREG_TEXUNIT1_LOC]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNIT1_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNIT2_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNIT2_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNIT2_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_009C|GPUREG_009C]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNIT2_LOC|GPUREG_TEXUNIT2_LOC]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNIT2_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_00A8|GPUREG_00A8]]
|?
|PICA_REG_TEXTURE3_PROTEX0
|-
| 00A9
| [[#GPUREG_00A9|GPUREG_00A9]]
|?
|PICA_REG_TEXTURE3_PROTEX1
|-
| 00AA
| [[#GPUREG_00AA|GPUREG_00AA]]
|?
|PICA_REG_TEXTURE3_PROTEX2
|-
| 00AB
| [[#GPUREG_00AB|GPUREG_00AB]]
|?
|PICA_REG_TEXTURE3_PROTEX3
|-
| 00AC
| [[#GPUREG_00AC|GPUREG_00AC]]
|?
|PICA_REG_TEXTURE3_PROTEX4
|-
| 00AD
| [[#GPUREG_00AD|GPUREG_00AD]]
|?
|PICA_REG_TEXTURE3_PROTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_00AF|GPUREG_00AF]]
|?
|PICA_REG_PROTEX_LUT
|-
| 00B0
| [[#GPUREG_00B0|GPUREG_00B0]]
| ?
|PICA_REG_PROTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_00B1|GPUREG_00B1]]
| ?
|PICA_REG_PROTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_00B2|GPUREG_00B2]]
| ?
|PICA_REG_PROTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_00B3|GPUREG_00B3]]
| ?
|PICA_REG_PROTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_00B4|GPUREG_00B4]]
| ?
|PICA_REG_PROTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_00B5|GPUREG_00B5]]
| ?
|PICA_REG_PROTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_00B6|GPUREG_00B6]]
| ?
|PICA_REG_PROTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_00B7|GPUREG_00B7]]
| ?
|PICA_REG_PROTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENV0_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENV0_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENV0_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENV0_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENV0_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENV1_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENV1_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENV1_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENV1_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENV1_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENV2_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENV2_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENV2_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENV2_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENV2_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENV3_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENV3_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENV3_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENV3_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENV3_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_00E1|GPUREG_00E1]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_00E4|GPUREG_00E4]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_00E5|GPUREG_00E5]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_00E6|GPUREG_00E6]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_00E8|GPUREG_00E8]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_00E9|GPUREG_00E9]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_00EA|GPUREG_00EA]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_00EB|GPUREG_00EB]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_00EC|GPUREG_00EC]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_00ED|GPUREG_00ED]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_00EE|GPUREG_00EE]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_00EF|GPUREG_00EF]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENV4_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENV4_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENV4_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENV4_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENV4_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENV5_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENV5_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENV5_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENV5_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENV5_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_BLEND_ENABLE|GPUREG_BLEND_ENABLE]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_CONFIG|GPUREG_BLEND_CONFIG]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGICOP_CONFIG|GPUREG_LOGICOP_CONFIG]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_ALPHATEST_CONFIG|GPUREG_ALPHATEST_CONFIG]]
|
|PICA_REG_FRAG_OP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_ACTION|GPUREG_STENCIL_ACTION]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTHTEST_CONFIG|GPUREG_DEPTHTEST_CONFIG]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_0118|GPUREG_0118]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_0120|GPUREG_0120]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_0121|GPUREG_0121]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_0122|GPUREG_0122]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_0123|GPUREG_0123]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_0124|GPUREG_0124]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_0126|GPUREG_0126]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_0130|GPUREG_0130]]
|?
|PICA_REG_FRAG_OP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|
|-
| 019B
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|
|-
| 01AB
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTx_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTx_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTx_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTx_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTx_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTx_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTx_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTx_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTx_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTx_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|
|-
| 01BB
| [[#GPUREG_LIGHTx_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATA|GPUREG_LIGHTING_LUT_DATA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFER0_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFER0_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFER0_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFER1_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFER1_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFER1_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFER2_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFER2_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFER2_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFER3_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFER3_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFER3_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFER4_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFER4_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFER4_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFER5_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFER5_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFER5_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFER6_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFER6_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFER6_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFER7_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFER7_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFER7_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFER8_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFER8_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFER8_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFER9_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFER9_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFER9_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFER10_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFER10_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFER10_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFER11_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFER11_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFER11_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_022D|GPUREG_022D]]
|
|
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_0231|GPUREG_0231]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_0242|GPUREG_0242]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_0244|GPUREG_0244]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_0245|GPUREG_0245]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_024A|GPUREG_024A]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_0251|GPUREG_0251]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_0252|GPUREG_0252]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_0253|GPUREG_0253]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_0254|GPUREG_0254]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_GSH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_GSH_INTUNIFORM_I0|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_GSH_INTUNIFORM_I1|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_GSH_INTUNIFORM_I2|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_GSH_INTUNIFORM_I3|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_GSH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_GSH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_GSH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0292
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0293
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0294
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0295
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0296
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0297
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0298
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA8
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_GSH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_GSH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_VSH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_VSH_INTUNIFORM_I0|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_VSH_INTUNIFORM_I1|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_VSH_INTUNIFORM_I2|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_VSH_INTUNIFORM_I3|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_VSH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_VSH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C2
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C3
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C4
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C5
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C6
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C7
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C8
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA8
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_VSH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_VSH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

== Texturing registers ==

== Framebuffer registers ==

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_DEPTHBUFFER_FORMAT ===

The format the current depth buffer should be written into. Following values are possible:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 1
| ?? seems to freeze the GPU
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil (stencil is within bit 24-31)
|}

=== GPUREG_COLORBUFFER_FORMAT ===

Describes the format of the current color buffer used for 3D rendering.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?)
|-
| 16-23
| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].

Color components are laid out in reverse byte order, with the most significant bits used first.
|}

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

When set to 0, use regular 8x8 tiling format for the framebuffer, compatible with textures. When set to 1, use a 32x32 tiling format. To untile the color buffer when using this format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

== Fragment lighting registers ==

=== GPUREG_LIGHTING_ENABLE0 ===

This register is set to 0 when fragment lighting is disabled, and to 1 when it is enabled.

=== GPUREG_LIGHTING_ENABLE1 ===

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Shadow factor enable, usually set to bit16 OR bit18 OR bit19
|-
| 1
| Unknown, set to 0
|-
| 2-3
| "Fresnel selector" (see below)
|-
| 4-7
| "Config", "Light env config" (see below)
|-
| 8-15
| Unknown, set to 4
|-
| 16
| "Shadow primary", 0=disabled, 1=enabled
|-
| 17
| "Shadow secondary", 0=disabled, 1=enabled
|-
| 18
| "Invert shadow", 0=disabled, 1=enabled
|-
| 19
| "Shadow alpha", 0=disabled, 1=enabled
|-
| 20-21
| Unknown, set to 0
|-
| 22-23
| "Bump selector"
|-
| 24-25
| "Shadow selector"
|-
| 26
| Unknown, set to 0
|-
| 27
| "Clamp highlights", 0=disabled, 1=enabled
|-
| 28-29
| "Bump mode", "Light env texy usage" (see below)
|-
| 30
| "Bump renorm", 0=enabled, 1=disabled
|-
| 31
| Unknown, set to 1
|}

Fresnel selector constants:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| NO_FRESNEL
|-
| 1
| PRI_ALPHA_FRESNEL
|-
| 2
| SEC_ALPHA_FRESNEL
|-
| 3
| PRI_SEC_ALPHA_FRESNEL
|}

Light env config constants:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| LIGHT_ENV_LAYER_CONFIG0
|-
| 1
| LIGHT_ENV_LAYER_CONFIG1
|-
| 2
| LIGHT_ENV_LAYER_CONFIG2
|-
| 3
| LIGHT_ENV_LAYER_CONFIG3
|-
| 4
| LIGHT_ENV_LAYER_CONFIG4
|-
| 5
| LIGHT_ENV_LAYER_CONFIG5
|-
| 6
| LIGHT_ENV_LAYER_CONFIG6
|-
| 8 (sic)
| LIGHT_ENV_LAYER_CONFIG7
|}

Bump mode constants:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| BUMP_NOT_USED
|-
| 1
| BUMP_AS_BUMP
|-
| 2
| BUMP_AS_TANG
|}

Bit 30 is set when bump mode is not zero.

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Disable bit for frag light source 0 shadows
|-
| 1
| Disable bit for frag light source 1 shadows
|-
| 2
| Disable bit for frag light source 2 shadows
|-
| 3
| Disable bit for frag light source 3 shadows
|-
| 4
| Disable bit for frag light source 4 shadows
|-
| 5
| Disable bit for frag light source 5 shadows
|-
| 6
| Disable bit for frag light source 6 shadows
|-
| 7
| Disable bit for frag light source 7 shadows
|-
| 8
| Disable bit for frag light source 0 spot
|-
| 9
| Disable bit for frag light source 1 spot
|-
| 10
| Disable bit for frag light source 2 spot
|-
| 11
| Disable bit for frag light source 3 spot
|-
| 12
| Disable bit for frag light source 4 spot
|-
| 13
| Disable bit for frag light source 5 spot
|-
| 14
| Disable bit for frag light source 6 spot
|-
| 15
| Disable bit for frag light source 7 spot
|-
| 16
| Disable bit for lut_D0
|-
| 17
| Disable bit for lut_D1
|-
| 18
| Unknown, set to 1
|-
| 19
| Disable bit for lut_FR
|-
| 20
| Disable bit for lut_RB
|-
| 21
| Disable bit for lut_RG
|-
| 22
| Disable bit for lut_RR
|-
| 23
| Unknown, set to 1
|-
| 24
| Disable bit for frag light source 0 distance attenuation
|-
| 25
| Disable bit for frag light source 1 distance attenuation
|-
| 26
| Disable bit for frag light source 2 distance attenuation
|-
| 27
| Disable bit for frag light source 3 distance attenuation
|-
| 28
| Disable bit for frag light source 4 distance attenuation
|-
| 29
| Disable bit for frag light source 5 distance attenuation
|-
| 30
| Disable bit for frag light source 6 distance attenuation
|-
| 31
| Disable bit for frag light source 7 distance attenuation
|}

=== GPUREG_LIGHTING_NUM_LIGHTS ===

The number of active lights minus one (0..7) is written to this register.

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| ID of the 1st enabled light (0..7)
|-
| 4-6
| ID of the 2nd enabled light (0..7)
|-
| 8-10
| ID of the 3rd enabled light (0..7)
|-
| 12-14
| ID of the 4th enabled light (0..7)
|-
| 16-18
| ID of the 5th enabled light (0..7)
|-
| 20-22
| ID of the 6th enabled light (0..7)
|-
| 24-26
| ID of the 7th enabled light (0..7)
|-
| 28-30
| ID of the 8th enabled light (0..7)
|}

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Input selector for lut_D0
|-
| 4-7
| Input selector for lut_D1
|-
| 8-11
| Input selector for lut_SP
|-
| 12-15
| Input selector for lut_FR
|-
| 16-19
| Input selector for lut_RB
|-
| 20-23
| Input selector for lut_RG
|-
| 24-27
| Input selector for lut_RR
|-
| 28-31
| Input selector for lut_DA
|}

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| abs() flag for the input of lut_D0 (0=enabled, 1=disabled)
|-
| 5
| abs() flag for the input of lut_D1 (0=enabled, 1=disabled)
|-
| 9
| abs() flag for the input of lut_SP (0=enabled, 1=disabled)
|-
| 13
| abs() flag for the input of lut_FR (0=enabled, 1=disabled)
|-
| 17
| abs() flag for the input of lut_RB (0=enabled, 1=disabled)
|-
| 21
| abs() flag for the input of lut_RG (0=enabled, 1=disabled)
|-
| 25
| abs() flag for the input of lut_RR (0=enabled, 1=disabled)
|-
| 29
| abs() flag for the input of lut_DA (0=enabled, 1=disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Scaler selector for lut_D0
|-
| 4-7
| Scaler selector for lut_D1
|-
| 8-11
| Scaler selector for lut_SP
|-
| 12-15
| Scaler selector for lut_FR
|-
| 16-19
| Scaler selector for lut_RB
|-
| 20-23
| Scaler selector for lut_RG
|-
| 24-27
| Scaler selector for lut_RR
|-
| 28-31
| Scaler selector for lut_DA
|}

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

This register controls the scaling that is applied to the output of a LUT.

=== GPUREG_LIGHTING_LUT_INDEX ===

This register controls which LUT and what offset into it the LUT_DATA register writes to.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Starting entry offset (0...255)
|-
| 8-10
| LUT ID (context=0) or Light ID (context=1,2)
|-
| 11-12
| Context ID
|}

LUT ID values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| lut_D0
|-
| 1
| lut_D1
|-
| 3
| lut_FR
|-
| 4
| lut_RB
|-
| 5
| lut_RG
|-
| 6
| lut_RR
|}

Context ID values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| LUTs common to all lights - writes to the LUT selected by the ID
|-
| 1
| lut_SP - writes to the LUT specific to the selected light
|-
| 2
| lut_DA - writes to the LUT specific to the selected light
|}

=== GPUREG_LIGHTING_LUT_DATA ===

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Entry value (12bit fractional number; floatval = x / 4096; however 0xFFF is treated as 1.0)
|-
| 12-22
| Absolute value of the difference between the next entry and this entry (11bit fractional number; floatval = x / 2048; however 0x7FF is treated as 1.0)
|-
| 23
| Sign bit of the difference (0=positive, 1=negative)
|}

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Blue component (0..255)
|-
| 10-17
| Green component (0..255)
|-
| 20-27
| Red component (0..255)
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTx_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Light type (0 = positional light, 1 = directional light)
|-
| 1
| Two side diffuse (0=disable, 1=enable)
|-
| 2
| Geometric factor 0 (0=disable, 1=enable)
|-
| 3
| Geometric factor 1 (0=disable, 1=enable)
|}

=== GPUREG_LIGHTx_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| X coordinate (float16 = 1.5.10)
|-
| 16-31
| Y coordinate (float16 = 1.5.10)
|}

These registers (along with _Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHTx_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Z coordinate (float16 = 1.5.10)
|}

These registers (along with _XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHTx_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| X coordinate (2.11 signed fixed point) (Usually the input value is negated)
|-
| 16-28
| Y coordinate (2.11 signed fixed point) (Usually the input value is negated)
|}

These registers (along with _Z) represent the spot direction (unitary) vector of the corresponding light .

=== GPUREG_LIGHTx_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| Z coordinate (2.11 signed fixed point) (Usually the input value is negated)
|}

These registers (along with _XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHTx_ATTENUATION_BIAS ===

These registers contain the distance attenuation bias value (float20 = 1.7.12) of the corresponding light.

=== GPUREG_LIGHTx_ATTENUATION_SCALE ===

These registers contain the distance attenuation scale value (float20 = 1.7.12) of the corresponding light.

=== GPUREG_LIGHTx_AMBIENT ===

These registers contain the ambient color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHTx_DIFFUSE ===

These registers contain the diffuse color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHTx_SPECULAR0 ===

These registers contain the specular0 color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHTx_SPECULAR1 ===

These registers contain the specular1 color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_specular1*lightX_specular1.

== Geometry pipeline registers ==

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
|-
| 8
| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''
|-
| 9-15
| No effect.
|-
| 16-23
| Unknown.
|-
| 24-31
| Unknown. Often set to 0.
|}

This register configures the geometry stage of the GPU pipeline.

=== GPUREG_FIXEDATTRIB_INDEX ===

See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline.
|}

=== GPUREG_FIXEDATTRIB_DATA ===

Accepts a packed 4-tuple of float24 values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].

If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]], but most games seem to write to it before every draw call.
|}

== Geometry shader registers ==

=== GPUREG_GSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the geometry shader unit's boolean registers.

=== GPUREG_GSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i0.w (u8, 0-255)
|}

This register is used to set the geometry shader's i0 integer register.

=== GPUREG_GSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i1.w (u8, 0-255)
|}

This register is used to set the geometry shader's i1 integer register.

=== GPUREG_GSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i2.w (u8, 0-255)
|}

This register is used to set the geometry shader's i2 integer register.

=== GPUREG_GSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i3.w (u8, 0-255)
|}

This register is used to set the geometry shader's i3 integer register.

=== GPUREG_GSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 8 for geometry shaders.
|}

This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.

=== GPUREG_GSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Geometry shader unit entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 8th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 16th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_GSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|}

This register toggles the geometry shader unit's output registers.

=== GPUREG_GSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.

=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_GSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_GSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target geometry shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_GSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader instruction data.
|}

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_GSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target geometry shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.

=== GPUREG_GSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader operand descriptor data.
|}

This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

== Vertex shader registers ==

=== GPUREG_VSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of vertex shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of vertex shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of vertex shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of vertex shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of vertex shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of vertex shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of vertex shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of vertex shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the vertex shader unit's boolean registers.

=== GPUREG_VSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i0.w (u8, 0-255)
|}

This register is used to set the vertex shader's i0 integer register.

=== GPUREG_VSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i1.w (u8, 0-255)
|}

This register is used to set the vertex shader's i1 integer register.

=== GPUREG_VSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i2.w (u8, 0-255)
|}

This register is used to set the vertex shader's i2 integer register.

=== GPUREG_VSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i3.w (u8, 0-255)
|}

This register is used to set the vertex shader's i3 integer register.

=== GPUREG_VSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 0xA for vertex shaders.
|}

This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.

=== GPUREG_VSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Vertex shader entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 8th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 16th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_VSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|-
| 7
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
|-
| 8
| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
|-
| 9
| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
|-
| 10
| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
|-
| 11
| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
|-
| 12
| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
|-
| 13
| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
|-
| 14
| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
|-
| 15
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
|}

This register toggles the vertex shader units' output registers.

=== GPUREG_VSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.

=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_VSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_VSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target vertex shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_VSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader instruction data.
|}

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_VSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target vertex shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.

=== GPUREG_VSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader operand descriptor data.
|}

This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

[[Category:GPU]]

GSP Shared Memory

2015-09-07T05:57:14Z

Yuriks: /* Trigger Texture Copy */ Document Texture Copy command.

This page describes the structure of the GSP [[GSPGPU:RegisterInterruptRelayQueue|shared]] memory. GX commands and framebuffer info is stored here, and other unknown data.

=Interrupt info=
The Interrupt info structure is located at sharedmemvadr + process_gsp_index*0x40.

It is a list of interrupts (id's 0-6 exist).

{| class="wikitable" border="1"
|-
! Index Byte
! Description
|-
| 0x0
| Index of the last processed data (field size is 0x33) (must be updated manually)
|-
| 0x1
| To be processed datafields, (max 0x20 for PDC interrupts else the missed PDC filds are used,max 0x34 for all other if more interrupts happen and the Errorflag is 0 the Errorflag is set to 1)
|-
| 0x2
| Errorflag (if the first bit of Errorflag is set future PDC interrupts are ignored)
|-
| 0x3
| not used
|-
| 0x4-0x7
| missed PDC0
|-
| 0x8-0xB
| missed PDC1
|-
| 0xC-0x3F
| u8 Interrupttypefield (0=PSC0, 1=PSC1, 2=PDC0/VBlankTop (sent to all threads), 3=PDC1/VBlankBottom (sent to all threads), 4=PPF, 5=P3D, 6=DMA)
|}

=Framebuffer info=
The framebuffer info structure for the main LCD is located at sharedmemvadr + 0x200 + threadindex*0x80. The framebuffer info structure for the sub LCD is located at sharedmemvadr + 0x240 + threadindex*0x80.

==Framebuffer info header==
{| class="wikitable" border="1"
|-
! Index Byte
! Description
|-
| 0
| Framebuffer info [[GSPGPU:SetBufferSwap|entry]] index
|-
| 1
| Flag
|-
| 3-2
| Padding
|}

When a process sets this framebuffer info, it sets index to <nowiki>(index+1) & 1</nowiki>. Then it writes the framebuffer info entry, and sets flag to value 1. The GSP module loads this framebuffer info entry data into GSP state once the [[GPU]] finishes processing GX commands 3 or 4. Once the GSP module finishes loading this framebuffer info, it sets flag to value 0, then it will not load the framebuffer info again until flag is value 1. After loading this entry data into GSP state, the GSP module then writes this framebuffer state to the [[LCD]] registers. GSP module automatically updates the LCD framebuffer registers each time GX commands 3 or 4 finish, even when this shared memory data was not updated by the application.(GSP module toggles the active framebuffer register when automatically updating LCD registers, when shared memory data is not used)

The two 0x1C-byte framebuffer info entries are located at framebufferinfo+4.

=3D Slider and 3D [[GSPGPU:SetLedForceOff|LED]]=
See [[Configuration Memory]].

=Command Buffer Header=

The command buffer is located at sharedmem + 0x800 + [[GSPGPU:RegisterInterruptRelayQueue|threadindex]]*0x200. After writing the command data to shared memory, [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] must be used to trigger GSP processing for the command when the total commands field is value 1.

{| class="wikitable" border="1"
|-
! Index Byte
! Description
|-
| 0
| Current command index. This index is updated by GSP module after loading the command data, right before the command is processed. When this index is updated by GSP module, the total commands field is decreased by one as well.
|-
| 1
| Total commands to process, must not be value 0 when GSP module handles commands. This must be <=15 when writing a command to shared memory. This is incremented by the application when writing a command to shared memory, after increasing this value [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] is only used if this field is value 1.
|-
| 2
| Must not be value 1. When the error-code u32 is set, this u8 is set to value 0x80.
|-
| 3
| Bit0 must not be set
|-
| 4
| u32 Error code for the last GX command which failed
|}

=Command Header=
{| class="wikitable" border="1"
|-
! Index Byte
! Description
|-
| 0
| Command ID
|-
| 2-1
| ?
|-
| 3
| When non-zero GSP module may check flags for the specified cmdID, command handling is aborted when the flags are set. The corresponding flag for each CmdID is set once the command is handled by GSP module, this flag is likely cleared once the GPU finishes processing the command.
|}

The command is located at cmdbuf + 0x20 + cmdindex*0x20, the size of each command is 0x20-bytes. The command parameters are located at command+4. Addresses specified in parameters are application vaddrs, these are usually located in either the process GSP [[Memory_layout|heap]] or VRAM. For applications these addresses are normally located in the GSP heap, while for other processes these addresses are located in VRAM. Addresses/sizes specified in parameters except for cmd0 and cmd5 must be 8-byte [[GPU|aligned]].

=Commands=

== Trigger DMA Request ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x00
|-
| 1
| Source address
|-
| 2
| Destination address
|-
| 3
| Size
|-
| 6-4
| Unused
|-
| 7
| Flag: when source buffer is not located in VRAM and this flag is non-zero, svcFlushProcessDataCache is used with the source buffer.
|}

This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM.

== Trigger Command List Processing ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x01
|-
| 1
| Buffer address
|-
| 2
| Buffer size
|-
| 3
| Flag, bit0 is written to GSP module state
|-
| 6-4
| Unused
|-
| 7
| When non-zero, call svcFlushProcessDataCache() with the specified buffer
|}

This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU_Commands|GPU commands]].

== Trigger Memory Fill ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x02
|-
| 1
| Buf0 start address (0 = don't fill anything)
|-
| 2
| Buf0 value
|-
| 3
| Buf0 end address
|-
| 4
| Buf1 start address (0 = don't fill anything)
|-
| 5
| Buf1 value
|-
| 6
| Buf1 end address
|-
| 7
| The low u16 is control0, while the high u16 is control1 (?)
|}

This command converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.

The values of control0 and control1 give information about the type of memory fill. See [[GPU Registers#Memory Fill|here]] for more information about memory fill parameters.

== Trigger Display Transfer ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x03
|-
| 1
| Input framebuffer address
|-
| 2
| Output framebuffer address
|-
| 3
| Input framebuffer [[GPU|dimensions]]
|-
| 4
| Output framebuffer dimensions
|-
| 5
| [[GPU|Flags]], for applications this is 0x1001000 for the main screen, and 0x1000 for the sub screen.
|-
| 7-6
| Unused
|}

This command converts the specified addresses to physical addresses, then writes these physical addresses and parameters to the [[GPU]] registers at 0x1EF00C00. This GPU command copies the already rendered framebuffer data from the input GPU framebuffer address to the specified output LCD framebuffer. The input framebuffer is normally located in VRAM.

The GPU color buffer is stored in the same Z-curve (tiled) format as textures. By default, SetDisplayTransfer converts the given buffer from the tiled format to a linear format adapted to the LCD framebuffers.

Display transfers are performed asynchronously, so after requesting a display transfer you should wait for the PPF interrupt to fire before reading the output data.

Some color formats seem to require specific input / output sizes when performing a display transfer, doing an RGB5A1->RGBA4 display transfer would never fire the PPF interrupt with a 32x32 buffer, increasing the buffer to 128x128 made it fire correctly.

== Trigger Texture Copy ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x04
|-
| 1
| Input buffer address.
|-
| 2
| Output buffer address.
|-
| 3
| Total bytes to copy, not including gaps.
|-
| 4
| Bits 0-15: Size of input line, in bytes. Bits 16-31: Gap between input lines, in bytes.
|-
| 5
| Same as 4, but for the output.
|-
| 6
| Flags, corresponding to the [[GPU/External_Registers#Transfer_Engine|Transfer Engine flags]]. However, for TextureCopy commands, bit 3 is always set, bit 2 is set if any output dimension is smaller than the input, and other bits are always 0.
|-
| 7
| Unused
|}

This command is similar to cmd3. It also triggers the [[GPU/External_Registers#Transfer_Engine|GPU Transfer Engine]], but setting the TextureCopy parameters.

== Flush Cache Regions ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x05
|-
| 1
| Buf0 address
|-
| 2
| Buf0 size
|-
| 3
| Buf1 address
|-
| 4
| Buf1 size
|-
| 5
| Buf2 address
|-
| 6
| Buf2 size
|-
| 7
| Unused
|}

The application buffer addresses specified in the parameters are used with [[SVC|svcFlushProcessDataCache]]. The input buf0 size must not be zero. When buf1 size is zero, svcFlushProcessDataCache() for buf1 and buf2 are skipped. When buf2 size is zero, svcFlushProcessDataCache() for buf2 is skipped.

GSP Shared Memory

2015-09-07T05:50:44Z

Yuriks: /* Prepare Command List Processing */ Rename command

This page describes the structure of the GSP [[GSPGPU:RegisterInterruptRelayQueue|shared]] memory. GX commands and framebuffer info is stored here, and other unknown data.

=Interrupt info=
The Interrupt info structure is located at sharedmemvadr + process_gsp_index*0x40.

It is a list of interrupts (id's 0-6 exist).

{| class="wikitable" border="1"
|-
! Index Byte
! Description
|-
| 0x0
| Index of the last processed data (field size is 0x33) (must be updated manually)
|-
| 0x1
| To be processed datafields, (max 0x20 for PDC interrupts else the missed PDC filds are used,max 0x34 for all other if more interrupts happen and the Errorflag is 0 the Errorflag is set to 1)
|-
| 0x2
| Errorflag (if the first bit of Errorflag is set future PDC interrupts are ignored)
|-
| 0x3
| not used
|-
| 0x4-0x7
| missed PDC0
|-
| 0x8-0xB
| missed PDC1
|-
| 0xC-0x3F
| u8 Interrupttypefield (0=PSC0, 1=PSC1, 2=PDC0/VBlankTop (sent to all threads), 3=PDC1/VBlankBottom (sent to all threads), 4=PPF, 5=P3D, 6=DMA)
|}

=Framebuffer info=
The framebuffer info structure for the main LCD is located at sharedmemvadr + 0x200 + threadindex*0x80. The framebuffer info structure for the sub LCD is located at sharedmemvadr + 0x240 + threadindex*0x80.

==Framebuffer info header==
{| class="wikitable" border="1"
|-
! Index Byte
! Description
|-
| 0
| Framebuffer info [[GSPGPU:SetBufferSwap|entry]] index
|-
| 1
| Flag
|-
| 3-2
| Padding
|}

When a process sets this framebuffer info, it sets index to <nowiki>(index+1) & 1</nowiki>. Then it writes the framebuffer info entry, and sets flag to value 1. The GSP module loads this framebuffer info entry data into GSP state once the [[GPU]] finishes processing GX commands 3 or 4. Once the GSP module finishes loading this framebuffer info, it sets flag to value 0, then it will not load the framebuffer info again until flag is value 1. After loading this entry data into GSP state, the GSP module then writes this framebuffer state to the [[LCD]] registers. GSP module automatically updates the LCD framebuffer registers each time GX commands 3 or 4 finish, even when this shared memory data was not updated by the application.(GSP module toggles the active framebuffer register when automatically updating LCD registers, when shared memory data is not used)

The two 0x1C-byte framebuffer info entries are located at framebufferinfo+4.

=3D Slider and 3D [[GSPGPU:SetLedForceOff|LED]]=
See [[Configuration Memory]].

=Command Buffer Header=

The command buffer is located at sharedmem + 0x800 + [[GSPGPU:RegisterInterruptRelayQueue|threadindex]]*0x200. After writing the command data to shared memory, [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] must be used to trigger GSP processing for the command when the total commands field is value 1.

{| class="wikitable" border="1"
|-
! Index Byte
! Description
|-
| 0
| Current command index. This index is updated by GSP module after loading the command data, right before the command is processed. When this index is updated by GSP module, the total commands field is decreased by one as well.
|-
| 1
| Total commands to process, must not be value 0 when GSP module handles commands. This must be <=15 when writing a command to shared memory. This is incremented by the application when writing a command to shared memory, after increasing this value [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] is only used if this field is value 1.
|-
| 2
| Must not be value 1. When the error-code u32 is set, this u8 is set to value 0x80.
|-
| 3
| Bit0 must not be set
|-
| 4
| u32 Error code for the last GX command which failed
|}

=Command Header=
{| class="wikitable" border="1"
|-
! Index Byte
! Description
|-
| 0
| Command ID
|-
| 2-1
| ?
|-
| 3
| When non-zero GSP module may check flags for the specified cmdID, command handling is aborted when the flags are set. The corresponding flag for each CmdID is set once the command is handled by GSP module, this flag is likely cleared once the GPU finishes processing the command.
|}

The command is located at cmdbuf + 0x20 + cmdindex*0x20, the size of each command is 0x20-bytes. The command parameters are located at command+4. Addresses specified in parameters are application vaddrs, these are usually located in either the process GSP [[Memory_layout|heap]] or VRAM. For applications these addresses are normally located in the GSP heap, while for other processes these addresses are located in VRAM. Addresses/sizes specified in parameters except for cmd0 and cmd5 must be 8-byte [[GPU|aligned]].

=Commands=

== Trigger DMA Request ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x00
|-
| 1
| Source address
|-
| 2
| Destination address
|-
| 3
| Size
|-
| 6-4
| Unused
|-
| 7
| Flag: when source buffer is not located in VRAM and this flag is non-zero, svcFlushProcessDataCache is used with the source buffer.
|}

This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM.

== Trigger Command List Processing ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x01
|-
| 1
| Buffer address
|-
| 2
| Buffer size
|-
| 3
| Flag, bit0 is written to GSP module state
|-
| 6-4
| Unused
|-
| 7
| When non-zero, call svcFlushProcessDataCache() with the specified buffer
|}

This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU_Commands|GPU commands]].

== Trigger Memory Fill ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x02
|-
| 1
| Buf0 start address (0 = don't fill anything)
|-
| 2
| Buf0 value
|-
| 3
| Buf0 end address
|-
| 4
| Buf1 start address (0 = don't fill anything)
|-
| 5
| Buf1 value
|-
| 6
| Buf1 end address
|-
| 7
| The low u16 is control0, while the high u16 is control1 (?)
|}

This command converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.

The values of control0 and control1 give information about the type of memory fill. See [[GPU Registers#Memory Fill|here]] for more information about memory fill parameters.

== Trigger Display Transfer ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x03
|-
| 1
| Input framebuffer address
|-
| 2
| Output framebuffer address
|-
| 3
| Input framebuffer [[GPU|dimensions]]
|-
| 4
| Output framebuffer dimensions
|-
| 5
| [[GPU|Flags]], for applications this is 0x1001000 for the main screen, and 0x1000 for the sub screen.
|-
| 7-6
| Unused
|}

This command converts the specified addresses to physical addresses, then writes these physical addresses and parameters to the [[GPU]] registers at 0x1EF00C00. This GPU command copies the already rendered framebuffer data from the input GPU framebuffer address to the specified output LCD framebuffer. The input framebuffer is normally located in VRAM.

The GPU color buffer is stored in the same Z-curve (tiled) format as textures. By default, SetDisplayTransfer converts the given buffer from the tiled format to a linear format adapted to the LCD framebuffers.

Display transfers are performed asynchronously, so after requesting a display transfer you should wait for the PPF interrupt to fire before reading the output data.

Some color formats seem to require specific input / output sizes when performing a display transfer, doing an RGB5A1->RGBA4 display transfer would never fire the PPF interrupt with a 32x32 buffer, increasing the buffer to 128x128 made it fire correctly.

== Trigger Texture Copy ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x04
|-
| 1
| Input buffer address
|-
| 2
| Output buffer address
|-
| 3
| Size
|-
| 4
| Input [[GPU|dimensions]]?
|-
| 5
| Output dimensions?
|-
| 6
| Flags, normally this is 0x8, with bit2 optionally set when either of the dimensions fields are set.
|-
| 7
| Unused
|}

This command is similar to cmd3. It also writes to the [[GPU]] registers at 0x1EF00C00. It's unknown where the difference is.

== Flush Cache Regions ==
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| u8 CommandID is 0x05
|-
| 1
| Buf0 address
|-
| 2
| Buf0 size
|-
| 3
| Buf1 address
|-
| 4
| Buf1 size
|-
| 5
| Buf2 address
|-
| 6
| Buf2 size
|-
| 7
| Unused
|}

The application buffer addresses specified in the parameters are used with [[SVC|svcFlushProcessDataCache]]. The input buf0 size must not be zero. When buf1 size is zero, svcFlushProcessDataCache() for buf1 and buf2 are skipped. When buf2 size is zero, svcFlushProcessDataCache() for buf2 is skipped.

GPU/Internal Registers

2015-09-07T05:45:14Z

Yuriks: /* Framebuffer registers */ Document GPUREG_FRAMEBUFFER_BLOCK32

[[Category:GFX]]
(this page is hugely WIP)

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_0047|GPUREG_0047]]
|?
|PICA_REG_FRAG_OP_CLIP
|-
| 0048
| [[#GPUREG_0048|GPUREG_0048]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_0049|GPUREG_0049]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_004A|GPUREG_004A]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_004B|GPUREG_004B]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_O0|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_O1|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_O2|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_O3|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_O4|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_O5|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_O6|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_0061|GPUREG_0061]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_0062|GPUREG_0062]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_0063|GPUREG_0063]]
|
|
|-
| 0064
| [[#GPUREG_0064|GPUREG_0064]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_006A|GPUREG_006A]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_006D|GPUREG_006D]]
|?
|PICA_REG_FRAG_OP_WSCALE
|-
| 006E
| [[#GPUREG_FRAMEBUFFER_DIM2|GPUREG_FRAMEBUFFER_DIM2]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_006F|GPUREG_006F]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_ENABLE|GPUREG_TEXUNIT_ENABLE]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNIT0_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNIT0_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNIT0_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_0084|GPUREG_0084]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNIT0_LOC|GPUREG_TEXUNIT0_LOC]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_0086|GPUREG_0086]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_0087|GPUREG_0087]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_0088|GPUREG_0088]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_0089|GPUREG_0089]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_008A|GPUREG_008A]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_008B|GPUREG_008B]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNIT0_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_008F|GPUREG_008F]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNIT1_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNIT1_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNIT1_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_0094|GPUREG_0094]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNIT1_LOC|GPUREG_TEXUNIT1_LOC]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNIT1_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNIT2_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNIT2_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNIT2_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_009C|GPUREG_009C]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNIT2_LOC|GPUREG_TEXUNIT2_LOC]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNIT2_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_00A8|GPUREG_00A8]]
|?
|PICA_REG_TEXTURE3_PROTEX0
|-
| 00A9
| [[#GPUREG_00A9|GPUREG_00A9]]
|?
|PICA_REG_TEXTURE3_PROTEX1
|-
| 00AA
| [[#GPUREG_00AA|GPUREG_00AA]]
|?
|PICA_REG_TEXTURE3_PROTEX2
|-
| 00AB
| [[#GPUREG_00AB|GPUREG_00AB]]
|?
|PICA_REG_TEXTURE3_PROTEX3
|-
| 00AC
| [[#GPUREG_00AC|GPUREG_00AC]]
|?
|PICA_REG_TEXTURE3_PROTEX4
|-
| 00AD
| [[#GPUREG_00AD|GPUREG_00AD]]
|?
|PICA_REG_TEXTURE3_PROTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_00AF|GPUREG_00AF]]
|?
|PICA_REG_PROTEX_LUT
|-
| 00B0
| [[#GPUREG_00B0|GPUREG_00B0]]
| ?
|PICA_REG_PROTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_00B1|GPUREG_00B1]]
| ?
|PICA_REG_PROTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_00B2|GPUREG_00B2]]
| ?
|PICA_REG_PROTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_00B3|GPUREG_00B3]]
| ?
|PICA_REG_PROTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_00B4|GPUREG_00B4]]
| ?
|PICA_REG_PROTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_00B5|GPUREG_00B5]]
| ?
|PICA_REG_PROTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_00B6|GPUREG_00B6]]
| ?
|PICA_REG_PROTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_00B7|GPUREG_00B7]]
| ?
|PICA_REG_PROTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENV0_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENV0_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENV0_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENV0_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENV0_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENV1_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENV1_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENV1_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENV1_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENV1_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENV2_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENV2_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENV2_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENV2_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENV2_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENV3_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENV3_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENV3_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENV3_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENV3_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_00E1|GPUREG_00E1]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_00E4|GPUREG_00E4]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_00E5|GPUREG_00E5]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_00E6|GPUREG_00E6]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_00E8|GPUREG_00E8]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_00E9|GPUREG_00E9]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_00EA|GPUREG_00EA]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_00EB|GPUREG_00EB]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_00EC|GPUREG_00EC]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_00ED|GPUREG_00ED]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_00EE|GPUREG_00EE]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_00EF|GPUREG_00EF]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENV4_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENV4_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENV4_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENV4_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENV4_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENV5_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENV5_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENV5_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENV5_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENV5_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_BLEND_ENABLE|GPUREG_BLEND_ENABLE]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_CONFIG|GPUREG_BLEND_CONFIG]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGICOP_CONFIG|GPUREG_LOGICOP_CONFIG]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_ALPHATEST_CONFIG|GPUREG_ALPHATEST_CONFIG]]
|
|PICA_REG_FRAG_OP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_ACTION|GPUREG_STENCIL_ACTION]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTHTEST_CONFIG|GPUREG_DEPTHTEST_CONFIG]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_0118|GPUREG_0118]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_0120|GPUREG_0120]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_0121|GPUREG_0121]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_0122|GPUREG_0122]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_0123|GPUREG_0123]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_0124|GPUREG_0124]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_0126|GPUREG_0126]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_0130|GPUREG_0130]]
|?
|PICA_REG_FRAG_OP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_0140|GPUREG_0140]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_0141|GPUREG_0141]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_0142|GPUREG_0142]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_0143|GPUREG_0143]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_0144|GPUREG_0144]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_0145|GPUREG_0145]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_0146|GPUREG_0146]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_0147|GPUREG_0147]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_0149|GPUREG_0149]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_014A|GPUREG_014A]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_014B|GPUREG_014B]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_0150|GPUREG_0150]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_0151|GPUREG_0151]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_0152|GPUREG_0152]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_0153|GPUREG_0153]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_0154|GPUREG_0154]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_0155|GPUREG_0155]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_0156|GPUREG_0156]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_0157|GPUREG_0157]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_0159|GPUREG_0159]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_015A|GPUREG_015A]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_015B|GPUREG_015B]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_0160|GPUREG_0160]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_0161|GPUREG_0161]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_0162|GPUREG_0162]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_0163|GPUREG_0163]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_0164|GPUREG_0164]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_0165|GPUREG_0165]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_0166|GPUREG_0166]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_0167|GPUREG_0167]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_0169|GPUREG_0169]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_016A|GPUREG_016A]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_016B|GPUREG_016B]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_0170|GPUREG_0170]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_0171|GPUREG_0171]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_0172|GPUREG_0172]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_0173|GPUREG_0173]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_0174|GPUREG_0174]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_0175|GPUREG_0175]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_0176|GPUREG_0176]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_0177|GPUREG_0177]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_0179|GPUREG_0179]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_017A|GPUREG_017A]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_017B|GPUREG_017B]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_0180|GPUREG_0180]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_0181|GPUREG_0181]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_0182|GPUREG_0182]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_0183|GPUREG_0183]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_0184|GPUREG_0184]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_0185|GPUREG_0185]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_0186|GPUREG_0186]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_0187|GPUREG_0187]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_0189|GPUREG_0189]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_018A|GPUREG_018A]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_018B|GPUREG_018B]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_0190|GPUREG_0190]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_0191|GPUREG_0191]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_0192|GPUREG_0192]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_0193|GPUREG_0193]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_0194|GPUREG_0194]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_0195|GPUREG_0195]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_0196|GPUREG_0196]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_0197|GPUREG_0197]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_0199|GPUREG_0199]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_019A|GPUREG_019A]]
|
|
|-
| 019B
| [[#GPUREG_019B|GPUREG_019B]]
|
|
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_01A0|GPUREG_01A0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_01A1|GPUREG_01A1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_01A2|GPUREG_01A2]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_01A3|GPUREG_01A3]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_01A4|GPUREG_01A4]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_01A5|GPUREG_01A5]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_01A6|GPUREG_01A6]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_01A7|GPUREG_01A7]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_01A9|GPUREG_01A9]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_01AA|GPUREG_01AA]]
|
|
|-
| 01AB
| [[#GPUREG_01AB|GPUREG_01AB]]
|
|
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_01B0|GPUREG_01B0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_01B1|GPUREG_01B1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_01B2|GPUREG_01B2]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_01B3|GPUREG_01B3]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_01B4|GPUREG_01B4]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_01B5|GPUREG_01B5]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_01B6|GPUREG_01B6]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_01B7|GPUREG_01B7]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_01B9|GPUREG_01B9]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_01BA|GPUREG_01BA]]
|
|
|-
| 01BB
| [[#GPUREG_01BB|GPUREG_01BB]]
|
|
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_01C0|GPUREG_01C0]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_01C2|GPUREG_01C2]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_01C3|GPUREG_01C3]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_01C4|GPUREG_01C4]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_01C5|GPUREG_01C5]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_01C6|GPUREG_01C6]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_01C8|GPUREG_01C8]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_01C9|GPUREG_01C9]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_01CA|GPUREG_01CA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_01CB|GPUREG_01CB]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_01CC|GPUREG_01CC]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_01CD|GPUREG_01CD]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA8
|-
| 01CE
| [[#GPUREG_01CE|GPUREG_01CE]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_01CF|GPUREG_01CF]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_01D0|GPUREG_01D0]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_01D1|GPUREG_01D1]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_01D2|GPUREG_01D2]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_01D9|GPUREG_01D9]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFER0_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFER0_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFER0_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFER1_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFER1_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFER1_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFER2_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFER2_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFER2_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFER3_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFER3_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFER3_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFER4_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFER4_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFER4_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFER5_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFER5_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFER5_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFER6_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFER6_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFER6_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFER7_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFER7_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFER7_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFER8_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFER8_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFER8_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFER9_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFER9_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFER9_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFER10_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFER10_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFER10_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFER11_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFER11_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFER11_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_022D|GPUREG_022D]]
|
|
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_0231|GPUREG_0231]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_0242|GPUREG_0242]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_0244|GPUREG_0244]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_0245|GPUREG_0245]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_024A|GPUREG_024A]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_0251|GPUREG_0251]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_0252|GPUREG_0252]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_0253|GPUREG_0253]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_0254|GPUREG_0254]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_GSH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_GSH_INTUNIFORM_I0|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_GSH_INTUNIFORM_I1|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_GSH_INTUNIFORM_I2|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_GSH_INTUNIFORM_I3|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_GSH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_GSH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_GSH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0292
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0293
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0294
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0295
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0296
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0297
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0298
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA8
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_GSH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_GSH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_VSH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_VSH_INTUNIFORM_I0|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_VSH_INTUNIFORM_I1|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_VSH_INTUNIFORM_I2|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_VSH_INTUNIFORM_I3|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_VSH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_VSH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C2
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C3
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C4
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C5
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C6
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C7
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C8
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA8
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_VSH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_VSH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

== Texturing registers ==

== Framebuffer registers ==

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_DEPTHBUFFER_FORMAT ===

The format the current depth buffer should be written into. Following values are possible:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 1
| ?? seems to freeze the GPU
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil (stencil is within bit 24-31)
|}

=== GPUREG_COLORBUFFER_FORMAT ===

Describes the format of the current color buffer used for 3D rendering.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?)
|-
| 16-23
| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].

Color components are laid out in reverse byte order, with the most significant bits used first.
|}

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

When set to 0, use regular 8x8 tiling format for the framebuffer, compatible with textures. When set to 1, use a 32x32 tiling format. To untile the color buffer when using this format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

== Fragment lighting registers ==

=== GPUREG_01C4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Disable bit for frag light source 0 shadows
|-
| 1
| Disable bit for frag light source 1 shadows
|-
| 2
| Disable bit for frag light source 2 shadows
|-
| 3
| Disable bit for frag light source 3 shadows
|-
| 4
| Disable bit for frag light source 4 shadows
|-
| 5
| Disable bit for frag light source 5 shadows
|-
| 6
| Disable bit for frag light source 6 shadows
|-
| 7
| Disable bit for frag light source 7 shadows
|-
| 8
| Disable bit for frag light source 0 spot
|-
| 9
| Disable bit for frag light source 1 spot
|-
| 10
| Disable bit for frag light source 2 spot
|-
| 11
| Disable bit for frag light source 3 spot
|-
| 12
| Disable bit for frag light source 4 spot
|-
| 13
| Disable bit for frag light source 5 spot
|-
| 14
| Disable bit for frag light source 6 spot
|-
| 15
| Disable bit for frag light source 7 spot
|-
| 24
| Disable bit for frag light source 0 distance attenuation
|-
| 25
| Disable bit for frag light source 1 distance attenuation
|-
| 26
| Disable bit for frag light source 2 distance attenuation
|-
| 27
| Disable bit for frag light source 3 distance attenuation
|-
| 28
| Disable bit for frag light source 4 distance attenuation
|-
| 29
| Disable bit for frag light source 5 distance attenuation
|-
| 30
| Disable bit for frag light source 6 distance attenuation
|-
| 31
| Disable bit for frag light source 7 distance attenuation
|}

== Geometry pipeline registers ==

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
|-
| 8
| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''
|-
| 9-15
| No effect.
|-
| 16-23
| Unknown.
|-
| 24-31
| Unknown. Often set to 0.
|}

This register configures the geometry stage of the GPU pipeline.

=== GPUREG_FIXEDATTRIB_INDEX ===

See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline.
|}

=== GPUREG_FIXEDATTRIB_DATA ===

Accepts a packed 4-tuple of float24 values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].

If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]], but most games seem to write to it before every draw call.
|}

== Geometry shader registers ==

=== GPUREG_GSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the geometry shader unit's boolean registers.

=== GPUREG_GSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i0.w (u8, 0-255)
|}

This register is used to set the geometry shader's i0 integer register.

=== GPUREG_GSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i1.w (u8, 0-255)
|}

This register is used to set the geometry shader's i1 integer register.

=== GPUREG_GSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i2.w (u8, 0-255)
|}

This register is used to set the geometry shader's i2 integer register.

=== GPUREG_GSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i3.w (u8, 0-255)
|}

This register is used to set the geometry shader's i3 integer register.

=== GPUREG_GSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 8 for geometry shaders.
|}

This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.

=== GPUREG_GSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Geometry shader unit entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 8th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 16th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_GSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|}

This register toggles the geometry shader unit's output registers.

=== GPUREG_GSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.

=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_GSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_GSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target geometry shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_GSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader instruction data.
|}

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_GSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target geometry shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.

=== GPUREG_GSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader operand descriptor data.
|}

This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

== Vertex shader registers ==

=== GPUREG_VSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of vertex shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of vertex shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of vertex shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of vertex shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of vertex shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of vertex shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of vertex shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of vertex shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the vertex shader unit's boolean registers.

=== GPUREG_VSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i0.w (u8, 0-255)
|}

This register is used to set the vertex shader's i0 integer register.

=== GPUREG_VSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i1.w (u8, 0-255)
|}

This register is used to set the vertex shader's i1 integer register.

=== GPUREG_VSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i2.w (u8, 0-255)
|}

This register is used to set the vertex shader's i2 integer register.

=== GPUREG_VSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i3.w (u8, 0-255)
|}

This register is used to set the vertex shader's i3 integer register.

=== GPUREG_VSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 0xA for vertex shaders.
|}

This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.

=== GPUREG_VSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Vertex shader entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 8th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 16th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_VSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|-
| 7
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
|-
| 8
| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
|-
| 9
| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
|-
| 10
| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
|-
| 11
| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
|-
| 12
| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
|-
| 13
| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
|-
| 14
| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
|-
| 15
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
|}

This register toggles the vertex shader units' output registers.

=== GPUREG_VSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.

=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_VSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_VSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target vertex shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_VSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader instruction data.
|}

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_VSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target vertex shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.

=== GPUREG_VSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader operand descriptor data.
|}

This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

[[Category:GPU]]

GPU/Internal Registers

2015-09-07T05:41:01Z

Yuriks: /* Framebuffer registers (0x100-0x13F) */ Name reg 0x11B: GPUREG_FRAMEBUFFER_BLOCK32

[[Category:GFX]]
(this page is hugely WIP)

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_0047|GPUREG_0047]]
|?
|PICA_REG_FRAG_OP_CLIP
|-
| 0048
| [[#GPUREG_0048|GPUREG_0048]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_0049|GPUREG_0049]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_004A|GPUREG_004A]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_004B|GPUREG_004B]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_O0|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_O1|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_O2|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_O3|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_O4|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_O5|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_O6|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_0061|GPUREG_0061]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_0062|GPUREG_0062]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_0063|GPUREG_0063]]
|
|
|-
| 0064
| [[#GPUREG_0064|GPUREG_0064]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_006A|GPUREG_006A]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_006D|GPUREG_006D]]
|?
|PICA_REG_FRAG_OP_WSCALE
|-
| 006E
| [[#GPUREG_FRAMEBUFFER_DIM2|GPUREG_FRAMEBUFFER_DIM2]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_006F|GPUREG_006F]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_ENABLE|GPUREG_TEXUNIT_ENABLE]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNIT0_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNIT0_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNIT0_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_0084|GPUREG_0084]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNIT0_LOC|GPUREG_TEXUNIT0_LOC]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_0086|GPUREG_0086]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_0087|GPUREG_0087]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_0088|GPUREG_0088]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_0089|GPUREG_0089]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_008A|GPUREG_008A]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_008B|GPUREG_008B]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNIT0_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_008F|GPUREG_008F]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNIT1_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNIT1_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNIT1_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_0094|GPUREG_0094]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNIT1_LOC|GPUREG_TEXUNIT1_LOC]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNIT1_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNIT2_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNIT2_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNIT2_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_009C|GPUREG_009C]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNIT2_LOC|GPUREG_TEXUNIT2_LOC]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNIT2_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_00A8|GPUREG_00A8]]
|?
|PICA_REG_TEXTURE3_PROTEX0
|-
| 00A9
| [[#GPUREG_00A9|GPUREG_00A9]]
|?
|PICA_REG_TEXTURE3_PROTEX1
|-
| 00AA
| [[#GPUREG_00AA|GPUREG_00AA]]
|?
|PICA_REG_TEXTURE3_PROTEX2
|-
| 00AB
| [[#GPUREG_00AB|GPUREG_00AB]]
|?
|PICA_REG_TEXTURE3_PROTEX3
|-
| 00AC
| [[#GPUREG_00AC|GPUREG_00AC]]
|?
|PICA_REG_TEXTURE3_PROTEX4
|-
| 00AD
| [[#GPUREG_00AD|GPUREG_00AD]]
|?
|PICA_REG_TEXTURE3_PROTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_00AF|GPUREG_00AF]]
|?
|PICA_REG_PROTEX_LUT
|-
| 00B0
| [[#GPUREG_00B0|GPUREG_00B0]]
| ?
|PICA_REG_PROTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_00B1|GPUREG_00B1]]
| ?
|PICA_REG_PROTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_00B2|GPUREG_00B2]]
| ?
|PICA_REG_PROTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_00B3|GPUREG_00B3]]
| ?
|PICA_REG_PROTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_00B4|GPUREG_00B4]]
| ?
|PICA_REG_PROTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_00B5|GPUREG_00B5]]
| ?
|PICA_REG_PROTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_00B6|GPUREG_00B6]]
| ?
|PICA_REG_PROTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_00B7|GPUREG_00B7]]
| ?
|PICA_REG_PROTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENV0_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENV0_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENV0_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENV0_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENV0_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENV1_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENV1_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENV1_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENV1_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENV1_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENV2_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENV2_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENV2_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENV2_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENV2_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENV3_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENV3_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENV3_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENV3_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENV3_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_00E1|GPUREG_00E1]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_00E4|GPUREG_00E4]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_00E5|GPUREG_00E5]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_00E6|GPUREG_00E6]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_00E8|GPUREG_00E8]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_00E9|GPUREG_00E9]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_00EA|GPUREG_00EA]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_00EB|GPUREG_00EB]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_00EC|GPUREG_00EC]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_00ED|GPUREG_00ED]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_00EE|GPUREG_00EE]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_00EF|GPUREG_00EF]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENV4_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENV4_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENV4_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENV4_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENV4_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENV5_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENV5_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENV5_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENV5_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENV5_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_BLEND_ENABLE|GPUREG_BLEND_ENABLE]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_CONFIG|GPUREG_BLEND_CONFIG]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGICOP_CONFIG|GPUREG_LOGICOP_CONFIG]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_ALPHATEST_CONFIG|GPUREG_ALPHATEST_CONFIG]]
|
|PICA_REG_FRAG_OP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_ACTION|GPUREG_STENCIL_ACTION]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTHTEST_CONFIG|GPUREG_DEPTHTEST_CONFIG]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_0118|GPUREG_0118]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_0120|GPUREG_0120]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_0121|GPUREG_0121]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_0122|GPUREG_0122]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_0123|GPUREG_0123]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_0124|GPUREG_0124]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_0126|GPUREG_0126]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_0130|GPUREG_0130]]
|?
|PICA_REG_FRAG_OP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_0140|GPUREG_0140]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_0141|GPUREG_0141]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_0142|GPUREG_0142]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_0143|GPUREG_0143]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_0144|GPUREG_0144]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_0145|GPUREG_0145]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_0146|GPUREG_0146]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_0147|GPUREG_0147]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_0149|GPUREG_0149]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_014A|GPUREG_014A]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_014B|GPUREG_014B]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_0150|GPUREG_0150]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_0151|GPUREG_0151]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_0152|GPUREG_0152]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_0153|GPUREG_0153]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_0154|GPUREG_0154]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_0155|GPUREG_0155]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_0156|GPUREG_0156]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_0157|GPUREG_0157]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_0159|GPUREG_0159]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_015A|GPUREG_015A]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_015B|GPUREG_015B]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_0160|GPUREG_0160]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_0161|GPUREG_0161]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_0162|GPUREG_0162]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_0163|GPUREG_0163]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_0164|GPUREG_0164]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_0165|GPUREG_0165]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_0166|GPUREG_0166]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_0167|GPUREG_0167]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_0169|GPUREG_0169]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_016A|GPUREG_016A]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_016B|GPUREG_016B]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_0170|GPUREG_0170]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_0171|GPUREG_0171]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_0172|GPUREG_0172]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_0173|GPUREG_0173]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_0174|GPUREG_0174]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_0175|GPUREG_0175]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_0176|GPUREG_0176]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_0177|GPUREG_0177]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_0179|GPUREG_0179]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_017A|GPUREG_017A]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_017B|GPUREG_017B]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_0180|GPUREG_0180]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_0181|GPUREG_0181]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_0182|GPUREG_0182]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_0183|GPUREG_0183]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_0184|GPUREG_0184]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_0185|GPUREG_0185]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_0186|GPUREG_0186]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_0187|GPUREG_0187]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_0189|GPUREG_0189]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_018A|GPUREG_018A]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_018B|GPUREG_018B]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_0190|GPUREG_0190]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_0191|GPUREG_0191]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_0192|GPUREG_0192]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_0193|GPUREG_0193]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_0194|GPUREG_0194]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_0195|GPUREG_0195]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_0196|GPUREG_0196]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_0197|GPUREG_0197]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_0199|GPUREG_0199]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_019A|GPUREG_019A]]
|
|
|-
| 019B
| [[#GPUREG_019B|GPUREG_019B]]
|
|
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_01A0|GPUREG_01A0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_01A1|GPUREG_01A1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_01A2|GPUREG_01A2]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_01A3|GPUREG_01A3]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_01A4|GPUREG_01A4]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_01A5|GPUREG_01A5]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_01A6|GPUREG_01A6]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_01A7|GPUREG_01A7]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_01A9|GPUREG_01A9]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_01AA|GPUREG_01AA]]
|
|
|-
| 01AB
| [[#GPUREG_01AB|GPUREG_01AB]]
|
|
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_01B0|GPUREG_01B0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_01B1|GPUREG_01B1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_01B2|GPUREG_01B2]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_01B3|GPUREG_01B3]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_01B4|GPUREG_01B4]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_01B5|GPUREG_01B5]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_01B6|GPUREG_01B6]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_01B7|GPUREG_01B7]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_01B9|GPUREG_01B9]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_01BA|GPUREG_01BA]]
|
|
|-
| 01BB
| [[#GPUREG_01BB|GPUREG_01BB]]
|
|
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_01C0|GPUREG_01C0]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_01C2|GPUREG_01C2]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_01C3|GPUREG_01C3]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_01C4|GPUREG_01C4]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_01C5|GPUREG_01C5]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_01C6|GPUREG_01C6]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_01C8|GPUREG_01C8]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_01C9|GPUREG_01C9]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_01CA|GPUREG_01CA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_01CB|GPUREG_01CB]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_01CC|GPUREG_01CC]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_01CD|GPUREG_01CD]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA8
|-
| 01CE
| [[#GPUREG_01CE|GPUREG_01CE]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_01CF|GPUREG_01CF]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_01D0|GPUREG_01D0]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_01D1|GPUREG_01D1]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_01D2|GPUREG_01D2]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_01D9|GPUREG_01D9]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFER0_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFER0_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFER0_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFER1_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFER1_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFER1_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFER2_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFER2_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFER2_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFER3_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFER3_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFER3_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFER4_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFER4_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFER4_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFER5_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFER5_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFER5_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFER6_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFER6_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFER6_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFER7_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFER7_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFER7_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFER8_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFER8_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFER8_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFER9_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFER9_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFER9_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFER10_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFER10_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFER10_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFER11_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFER11_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFER11_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_022D|GPUREG_022D]]
|
|
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_0231|GPUREG_0231]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_0242|GPUREG_0242]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_0244|GPUREG_0244]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_0245|GPUREG_0245]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_024A|GPUREG_024A]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_0251|GPUREG_0251]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_0252|GPUREG_0252]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_0253|GPUREG_0253]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_0254|GPUREG_0254]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_GSH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_GSH_INTUNIFORM_I0|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_GSH_INTUNIFORM_I1|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_GSH_INTUNIFORM_I2|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_GSH_INTUNIFORM_I3|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_GSH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_GSH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_GSH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0292
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0293
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0294
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0295
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0296
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0297
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0298
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA8
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_GSH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_GSH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_VSH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_VSH_INTUNIFORM_I0|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_VSH_INTUNIFORM_I1|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_VSH_INTUNIFORM_I2|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_VSH_INTUNIFORM_I3|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_VSH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_VSH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C2
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C3
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C4
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C5
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C6
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C7
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C8
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA8
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_VSH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_VSH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

== Texturing registers ==

== Framebuffer registers ==

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_DEPTHBUFFER_FORMAT ===

The format the current depth buffer should be written into. Following values are possible:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 1
| ?? seems to freeze the GPU
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil (stencil is within bit 24-31)
|}

=== GPUREG_COLORBUFFER_FORMAT ===

Describes the format of the current color buffer used for 3D rendering.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?)
|-
| 16-23
| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].

Color components are laid out in reverse byte order, with the most significant bits used first.
|}

== Fragment lighting registers ==

=== GPUREG_01C4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Disable bit for frag light source 0 shadows
|-
| 1
| Disable bit for frag light source 1 shadows
|-
| 2
| Disable bit for frag light source 2 shadows
|-
| 3
| Disable bit for frag light source 3 shadows
|-
| 4
| Disable bit for frag light source 4 shadows
|-
| 5
| Disable bit for frag light source 5 shadows
|-
| 6
| Disable bit for frag light source 6 shadows
|-
| 7
| Disable bit for frag light source 7 shadows
|-
| 8
| Disable bit for frag light source 0 spot
|-
| 9
| Disable bit for frag light source 1 spot
|-
| 10
| Disable bit for frag light source 2 spot
|-
| 11
| Disable bit for frag light source 3 spot
|-
| 12
| Disable bit for frag light source 4 spot
|-
| 13
| Disable bit for frag light source 5 spot
|-
| 14
| Disable bit for frag light source 6 spot
|-
| 15
| Disable bit for frag light source 7 spot
|-
| 24
| Disable bit for frag light source 0 distance attenuation
|-
| 25
| Disable bit for frag light source 1 distance attenuation
|-
| 26
| Disable bit for frag light source 2 distance attenuation
|-
| 27
| Disable bit for frag light source 3 distance attenuation
|-
| 28
| Disable bit for frag light source 4 distance attenuation
|-
| 29
| Disable bit for frag light source 5 distance attenuation
|-
| 30
| Disable bit for frag light source 6 distance attenuation
|-
| 31
| Disable bit for frag light source 7 distance attenuation
|}

== Geometry pipeline registers ==

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
|-
| 8
| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''
|-
| 9-15
| No effect.
|-
| 16-23
| Unknown.
|-
| 24-31
| Unknown. Often set to 0.
|}

This register configures the geometry stage of the GPU pipeline.

=== GPUREG_FIXEDATTRIB_INDEX ===

See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline.
|}

=== GPUREG_FIXEDATTRIB_DATA ===

Accepts a packed 4-tuple of float24 values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].

If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]], but most games seem to write to it before every draw call.
|}

== Geometry shader registers ==

=== GPUREG_GSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the geometry shader unit's boolean registers.

=== GPUREG_GSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i0.w (u8, 0-255)
|}

This register is used to set the geometry shader's i0 integer register.

=== GPUREG_GSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i1.w (u8, 0-255)
|}

This register is used to set the geometry shader's i1 integer register.

=== GPUREG_GSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i2.w (u8, 0-255)
|}

This register is used to set the geometry shader's i2 integer register.

=== GPUREG_GSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i3.w (u8, 0-255)
|}

This register is used to set the geometry shader's i3 integer register.

=== GPUREG_GSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 8 for geometry shaders.
|}

This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.

=== GPUREG_GSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Geometry shader unit entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 8th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 16th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_GSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|}

This register toggles the geometry shader unit's output registers.

=== GPUREG_GSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.

=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_GSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_GSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target geometry shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_GSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader instruction data.
|}

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_GSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target geometry shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.

=== GPUREG_GSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader operand descriptor data.
|}

This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

== Vertex shader registers ==

=== GPUREG_VSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of vertex shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of vertex shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of vertex shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of vertex shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of vertex shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of vertex shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of vertex shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of vertex shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the vertex shader unit's boolean registers.

=== GPUREG_VSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i0.w (u8, 0-255)
|}

This register is used to set the vertex shader's i0 integer register.

=== GPUREG_VSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i1.w (u8, 0-255)
|}

This register is used to set the vertex shader's i1 integer register.

=== GPUREG_VSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i2.w (u8, 0-255)
|}

This register is used to set the vertex shader's i2 integer register.

=== GPUREG_VSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i3.w (u8, 0-255)
|}

This register is used to set the vertex shader's i3 integer register.

=== GPUREG_VSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 0xA for vertex shaders.
|}

This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.

=== GPUREG_VSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Vertex shader entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 8th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 16th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_VSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|-
| 7
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
|-
| 8
| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
|-
| 9
| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
|-
| 10
| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
|-
| 11
| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
|-
| 12
| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
|-
| 13
| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
|-
| 14
| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
|-
| 15
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
|}

This register toggles the vertex shader units' output registers.

=== GPUREG_VSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.

=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_VSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_VSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target vertex shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_VSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader instruction data.
|}

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_VSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target vertex shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.

=== GPUREG_VSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader operand descriptor data.
|}

This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

[[Category:GPU]]

GPU/External Registers

2015-09-07T05:39:51Z

Yuriks: /* Flags Register - 0x1EF00C10 */ More info about the 32x32 block mode

This page describes the address range accessible from the ARM11, used to configure the basic GPU functionality. For information about the internal registers used for 3D rendering, see [[GPU/Internal Registers]].

== Map ==
{| class="wikitable" border="1"
! User VA
! PA
! Length
! Name
! Comments
|-
| 0x1EF00004
| 0x10400004
| 4
| ?
|
|-
| 0x1EF00010
| 0x10400010
| 16
| [[#Memory Fill|Memory Fill1]] "PSC0"
| GX command 2
|-
| 0x1EF00020
| 0x10400020
| 16
| [[#Memory Fill|Memory Fill2]] "PSC1"
| GX command 2
|-
| 0x1EF00030
| 0x10400030
| 4
| ?
|
|-
| 0x1EF00034
| 0x10400034
| 4
| GPU Busy
| Bit31 = cmd-list busy, bit27 = PSC0 busy, bit26 = PSC1 busy.
|-
| 0x1EF00050
| 0x10400050
| 4
| ?
| Writes 0x22221200 on GPU init.
|-
| 0x1EF00054
| 0x10400054
| 4
| ?
| Writes 0xFF2 on GPU init.
|-
| 0x1EF00400
| 0x10400400
| 0x100
| [[#Framebuffer_Setup|Framebuffer Setup]] "PDC0" (top screen)
|
|-
| 0x1EF00500
| 0x10400500
| 0x100
| [[#Framebuffer_Setup|Framebuffer Setup]] "PDC1" (bottom)
|
|-
| 0x1EF00C00
| 0x10400C00
| ?
| [[#Transfer_Engine|Transfer Engine]] "DMA"
|
|-
| 0x1EF01000
| 0x10401000
| 0x4
| ?
| Writes 0 on GPU init and before the Command List is used
|-
| 0x1EF01080
| 0x10401080
| 0x4
| ?
| Writes 0x12345678 on GPU init.
|-
| 0x1EF010C0
| 0x104010C0
| 0x4
| ?
| Writes 0xFFFFFFF0 on GPU init.
|-
| 0x1EF010D0
| 0x104010D0
| 0x4
| ?
| Writes 1 on GPU init.
|-
| 0x1EF014??
| 0x104014??
| 0x14
| "PPF" ?
|
|-
| 0x1EF018E0
| 0x104018E0
| 0x14
| [[#Command_List|Command List]] "P3D"
|
|}

== Memory Fill ==
{| class="wikitable" border="1"
! User VA
! Description
|-
| 0x1EF000X0
| Buffer start physaddr >> 3
|-
| 0x1EF000X4
| Buffer end physaddr >> 3
|-
| 0x1EF000X8
| Fill value
|-
| 0x1EF000XC
| Control. bit0: start/busy, bit1: finished, bit8-9: fill-width (0=16bit, 1=3=24bit, 2=32bit)
|}

Memory fills are used to initialize buffers in memory with a given value, similar to memset. A memory fill is triggered by setting bit0 in the control register. Doing so aborts any running memory fills on that filling unit. Upon completion, the hardware unsets bit0 and sets bit1 and fires interrupt PSC0.

These registers are used by [[GSP Shared Memory#GX SetMemoryFill|GX SetMemoryFill]].

== LCD Source Framebuffer Setup ==
{| class="wikitable" border="1"
! Offset
! Length
! Name
! Comments
|-
| 0x5C
| 4
| Framebuffer width & height
| Lower 16 bits: width, upper 16 bits: height
|-
| 0x68
| 4
| Framebuffer A first address
| For top screen, this is the left eye 3D framebuffer.
|-
| 0x6C
| 4
| Framebuffer A second address
| For top screen, this is the left eye 3D framebuffer.
|-
| 0x70
| 4
| Framebuffer format
| Bit0-15: framebuffer format, bit16-31: unknown
|-
| 0x78
| 4
| Framebuffer select
| Bit0: which framebuffer to display, bit1-7: unknown
|-
| 0x90
| 4
| Framebuffer stride
| Distance in bytes between the start of two framebuffer rows (must be a multiple of 8).
|-
| 0x94
| 4
| Framebuffer B first address
| For top screen, this is the right eye 3D framebuffer. Unused for bottom screen.
|-
| 0x98
| 4
| Framebuffer B second address
| For top screen, this is the right eye 3D framebuffer. Unused for bottom screen.
|}

=== Framebuffer format ===
{| class="wikitable" border="1"
|-
! Bit
! Description
|-
| 2-0
| Color format
|-
| 3
| ?
|-
| 4
| Unused?
|-
| 5
| Enable parallax barrier (i.e. 3D).
|-
| 6
| 1 = main screen, 0 = sub screen. However if bit5 is set, this bit is cleared.
|-
| 7
| ?
|-
| 9-8
| Value 1 = unknown: get rid of rainbow strip on top of screen, 3 = unknown: black screen.
|-
| 15-10
| Unused?
|}

GSP module only allows the LCD stereoscopy to be enabled when bit5=1 and bit6=0 here. When GSP module updates this register, GSP module will automatically disable the stereoscopy if those bits are not set for enabling stereoscopy.

=== Framebuffer color formats ===
{| class="wikitable" border="1"
|-
! Value
! Description
|-
| 0
| GL_RGBA8_OES
|-
| 1
| GL_RGB8_OES
|-
| 2
| GL_RGB565_OES
|-
| 3
| GL_RGB5_A1_OES
|-
| 4
| GL_RGBA4_OES
|}
Color components are laid out in reverse byte order, with the most significant bits used first (i.e. non-24-bit pixels are stored as a little-endian values). For instance, a raw data stream of two GL_RGB565_OES pixels looks like GGGBBBBB RRRRRGGG GGGBBBBB RRRRRGGG.

== Transfer Engine ==
{| class="wikitable" border="1"
! Register address
! Description
|-
| 0x1EF00C00
| Input physical address >> 3
|-
| 0x1EF00C04
| Output physical address >> 3
|-
| 0x1EF00C08
| DisplayTransfer output width (bits 0-15) and height (bits 16-31).
|-
| 0x1EF00C0C
| DisplayTransfer input width and height.
|-
| 0x1EF00C10
| Transfer flags. (See below)
|-
| 0x1EF00C14
| GSP module writes value 0 here prior to writing to 0x1EF00C18, for cmd3.
|-
| 0x1EF00C18
| Setting bit0 starts the transfer. Upon completion, bit0 is unset and bit8 is set.
|-
| 0x1EF00C20
| TextureCopy total amount of data to copy, in bytes.
|-
| 0x1EF00C24
| TextureCopy input line width (bits 0-15) and gap (bits 16-31), in bytes.
|-
| 0x1EF00C28
| TextureCopy output line width and gap.
|}

These registers are used by [[GSP_Shared_Memory|GX command]] 3 and 4. For cmd4, *0x1EF00C18 |= 1 is used instead of just writing value 1. The DisplayTransfer registers are only used if bit 3 of the flags is unset and ignored otherwise. The TextureCopy registers are likewise only used if bit 3 is set, and ignored otherwise.

==== Flags Register - 0x1EF00C10 ====
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0
| When set, the framebuffer data is flipped vertically.
|-
| 1
| When set, the input framebuffer is treated as linear and converted to tiled in the output, converts tiled->linear when unset.
|-
| 2
| This bit is required when the output width is less than the input width for the hardware to properly crop the lines, otherwise the output will be mis-aligned.
|-
| 3
| Uses a TextureCopy mode transfer. See below for details.
|-
| 4
| Not writable
|-
| 5
| Don't perform tiled-linear conversion. Incompatible with bit 1, so only tiled-tiled transfers can be done, not linear-linear.
|-
| 7-6
| Not writable
|-
| 10-8
| Input framebuffer color format, value0 and value1 are the same as the [[GPU Registers#Framebuffer_color_formats|LCD Source Framebuffer Formats]] (usually zero)
|-
| 11
| Not writable
|-
| 14-12
| Output framebuffer color format
|-
| 15
| Not writable
|-
| 16
| Use 32x32 block tiling mode, instead of the usual 8x8 one. Output dimensions must be multiples of 32, even if cropping with bit 2 set above.
|-
| 17-23
| Not writable
|-
| 24-25
| Scale down the input image using a box filter. 0 = No downscale, 1 = 2x1 downscale. 2 = 2x2 downscale, 3 = invalid
|-
| 31-26
| Not writable
|}

=== TextureCopy ===

When bit 3 of the control register is set, the hardware performs a TextureCopy-mode transfer. In this mode, all other bits of the control register (except for bit 2, which still needs to be set correctly) and the regular dimension registers are ignored, and no format conversions are done. Instead, it performs a raw data copy from the source to the destination, but with a configurable gap between lines. The total amount of bytes to copy is specified in the size register, and the hardware loops reading lines from the input and writing them to the output until this amount is copied. The "gap" specified in the input/output dimension register is the number of bytes to skip after each "width" bytes of the input/output, and is NOT counted towards the total size of the transfer.

By correctly calculating the input and output gap sizes it is possible to use this functionality to copy arbitrary sub-rectangles between differently-sized framebuffers or textures, which is one of its main uses over a regular no-conversion DisplayTransfer. When copying tiled textures/framebuffers it's important to remember that the contents of a tile are laid out sequentially in memory, and so this should be taken into account when calculating the transfer parameters.

Specifying invalid/junk values for the TextureCopy dimensions can result in the GPU hanging while attempting to process this TextureCopy.

== Command List ==
{| class="wikitable" border="1"
! Register address
! Description
|-
| 0x1EF018E0
| Buffer size in bytes >> 3
|-
| 0x1EF018E8
| Buffer physical address >> 3
|-
| 0x1EF018F0
| Setting bit0 to 1 enables processing GPU command execution. Upon completion, bit0 seems to be reset to 0.
|}

These 3 registers are used by [[GSP_Shared_Memory|GX command]] 1. This is used for [[GPU_Commands|GPU commands]].

== Framebuffers ==
These LCD framebuffers normally contain the last rendered frames from the GPU. The framebuffers are drawn from left-to-right, instead of top-to-bottom.(Thus the beginning of the framebuffer is drawn starting at the left side of the screen)

Both of the 3D screen left/right framebuffers are displayed regardless of the 3D slider's state, however when the 3D slider is set to "off" the 3D effect is disabled. Normally when the 3D slider's state is set to "off" the left/right framebuffer addresses are set to the same physical address. When the 3D effect is disabled and the left/right framebuffers are set to separate addresses, the LCD seems to alternate between displaying the left/right framebuffer each frame.

==== Init Values from nngxInitialize for Top Screen ====
* 0x1EF00400 = 0x1C2
* 0x1EF00404 = 0xD1
* 0x1EF00408 = 0x1C1
* 0x1EF0040C = 0x1C1
* 0x1EF00410 = 0
* 0x1EF00414 = 0xCF
* 0x1EF00418 = 0xD1
* 0x1EF0041C = 0x1C501C1
* 0x1EF00420 = 0x10000
* 0x1EF00424 = 0x19D
* 0x1EF00428 = 2
* 0x1EF0042C = 0x1C2
* 0x1EF00430 = 0x1C2
* 0x1EF00434 = 0x1C2
* 0x1EF00438 = 1
* 0x1EF0043C = 2
* 0x1EF00440 = 0x1960192
* 0x1EF00444 = 0
* 0x1EF00448 = 0
* 0x1EF0045C = 0x19000F0
* 0x1EF00460 = 0x1c100d1
* 0x1EF00464 = 0x1920002
* 0x1EF00470 = 0x80340
* 0x1EF0049C = 0

==== More Init Values from nngxInitialize for Top Screen ====
* 0x1EF00468 = 0x18300000, later changed by GSP module when updating state, framebuffer
* 0x1EF0046C = 0x18300000, later changed by GSP module when updating state, framebuffer
* 0x1EF00494 = 0x18300000
* 0x1EF00498 = 0x18300000
* 0x1EF00478 = 1, doesn't stay 1, read as 0
* 0x1EF00474 = 0x10501

[[Category:GPU]]

GPU/Internal Registers

2015-09-07T03:12:11Z

Yuriks: /* Framebuffer registers */ Document GPUREG_FRAMEBUFFER_INVALIDATE and _FLUSH

[[Category:GFX]]
(this page is hugely WIP)

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_0047|GPUREG_0047]]
|?
|PICA_REG_FRAG_OP_CLIP
|-
| 0048
| [[#GPUREG_0048|GPUREG_0048]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_0049|GPUREG_0049]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_004A|GPUREG_004A]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_004B|GPUREG_004B]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_O0|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_O1|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_O2|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_O3|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_O4|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_O5|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_O6|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_0061|GPUREG_0061]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_0062|GPUREG_0062]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_0063|GPUREG_0063]]
|
|
|-
| 0064
| [[#GPUREG_0064|GPUREG_0064]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_006A|GPUREG_006A]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_006D|GPUREG_006D]]
|?
|PICA_REG_FRAG_OP_WSCALE
|-
| 006E
| [[#GPUREG_FRAMEBUFFER_DIM2|GPUREG_FRAMEBUFFER_DIM2]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_006F|GPUREG_006F]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_ENABLE|GPUREG_TEXUNIT_ENABLE]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNIT0_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNIT0_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNIT0_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_0084|GPUREG_0084]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNIT0_LOC|GPUREG_TEXUNIT0_LOC]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_0086|GPUREG_0086]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_0087|GPUREG_0087]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_0088|GPUREG_0088]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_0089|GPUREG_0089]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_008A|GPUREG_008A]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_008B|GPUREG_008B]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNIT0_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_008F|GPUREG_008F]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNIT1_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNIT1_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNIT1_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_0094|GPUREG_0094]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNIT1_LOC|GPUREG_TEXUNIT1_LOC]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNIT1_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNIT2_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNIT2_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNIT2_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_009C|GPUREG_009C]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNIT2_LOC|GPUREG_TEXUNIT2_LOC]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNIT2_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_00A8|GPUREG_00A8]]
|?
|PICA_REG_TEXTURE3_PROTEX0
|-
| 00A9
| [[#GPUREG_00A9|GPUREG_00A9]]
|?
|PICA_REG_TEXTURE3_PROTEX1
|-
| 00AA
| [[#GPUREG_00AA|GPUREG_00AA]]
|?
|PICA_REG_TEXTURE3_PROTEX2
|-
| 00AB
| [[#GPUREG_00AB|GPUREG_00AB]]
|?
|PICA_REG_TEXTURE3_PROTEX3
|-
| 00AC
| [[#GPUREG_00AC|GPUREG_00AC]]
|?
|PICA_REG_TEXTURE3_PROTEX4
|-
| 00AD
| [[#GPUREG_00AD|GPUREG_00AD]]
|?
|PICA_REG_TEXTURE3_PROTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_00AF|GPUREG_00AF]]
|?
|PICA_REG_PROTEX_LUT
|-
| 00B0
| [[#GPUREG_00B0|GPUREG_00B0]]
| ?
|PICA_REG_PROTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_00B1|GPUREG_00B1]]
| ?
|PICA_REG_PROTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_00B2|GPUREG_00B2]]
| ?
|PICA_REG_PROTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_00B3|GPUREG_00B3]]
| ?
|PICA_REG_PROTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_00B4|GPUREG_00B4]]
| ?
|PICA_REG_PROTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_00B5|GPUREG_00B5]]
| ?
|PICA_REG_PROTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_00B6|GPUREG_00B6]]
| ?
|PICA_REG_PROTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_00B7|GPUREG_00B7]]
| ?
|PICA_REG_PROTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENV0_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENV0_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENV0_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENV0_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENV0_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENV1_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENV1_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENV1_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENV1_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENV1_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENV2_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENV2_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENV2_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENV2_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENV2_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENV3_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENV3_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENV3_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENV3_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENV3_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_00E1|GPUREG_00E1]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_00E4|GPUREG_00E4]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_00E5|GPUREG_00E5]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_00E6|GPUREG_00E6]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_00E8|GPUREG_00E8]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_00E9|GPUREG_00E9]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_00EA|GPUREG_00EA]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_00EB|GPUREG_00EB]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_00EC|GPUREG_00EC]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_00ED|GPUREG_00ED]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_00EE|GPUREG_00EE]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_00EF|GPUREG_00EF]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENV4_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENV4_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENV4_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENV4_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENV4_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENV5_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENV5_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENV5_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENV5_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENV5_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_BLEND_ENABLE|GPUREG_BLEND_ENABLE]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_CONFIG|GPUREG_BLEND_CONFIG]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGICOP_CONFIG|GPUREG_LOGICOP_CONFIG]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_ALPHATEST_CONFIG|GPUREG_ALPHATEST_CONFIG]]
|
|PICA_REG_FRAG_OP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_ACTION|GPUREG_STENCIL_ACTION]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTHTEST_CONFIG|GPUREG_DEPTHTEST_CONFIG]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_0118|GPUREG_0118]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_011B|GPUREG_011B]]
|?
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_0120|GPUREG_0120]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_0121|GPUREG_0121]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_0122|GPUREG_0122]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_0123|GPUREG_0123]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_0124|GPUREG_0124]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_0126|GPUREG_0126]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_0130|GPUREG_0130]]
|?
|PICA_REG_FRAG_OP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_0140|GPUREG_0140]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_0141|GPUREG_0141]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_0142|GPUREG_0142]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_0143|GPUREG_0143]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_0144|GPUREG_0144]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_0145|GPUREG_0145]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_0146|GPUREG_0146]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_0147|GPUREG_0147]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_0149|GPUREG_0149]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_014A|GPUREG_014A]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_014B|GPUREG_014B]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_0150|GPUREG_0150]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_0151|GPUREG_0151]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_0152|GPUREG_0152]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_0153|GPUREG_0153]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_0154|GPUREG_0154]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_0155|GPUREG_0155]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_0156|GPUREG_0156]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_0157|GPUREG_0157]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_0159|GPUREG_0159]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_015A|GPUREG_015A]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_015B|GPUREG_015B]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_0160|GPUREG_0160]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_0161|GPUREG_0161]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_0162|GPUREG_0162]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_0163|GPUREG_0163]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_0164|GPUREG_0164]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_0165|GPUREG_0165]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_0166|GPUREG_0166]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_0167|GPUREG_0167]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_0169|GPUREG_0169]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_016A|GPUREG_016A]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_016B|GPUREG_016B]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_0170|GPUREG_0170]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_0171|GPUREG_0171]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_0172|GPUREG_0172]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_0173|GPUREG_0173]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_0174|GPUREG_0174]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_0175|GPUREG_0175]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_0176|GPUREG_0176]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_0177|GPUREG_0177]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_0179|GPUREG_0179]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_017A|GPUREG_017A]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_017B|GPUREG_017B]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_0180|GPUREG_0180]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_0181|GPUREG_0181]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_0182|GPUREG_0182]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_0183|GPUREG_0183]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_0184|GPUREG_0184]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_0185|GPUREG_0185]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_0186|GPUREG_0186]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_0187|GPUREG_0187]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_0189|GPUREG_0189]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_018A|GPUREG_018A]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_018B|GPUREG_018B]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_0190|GPUREG_0190]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_0191|GPUREG_0191]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_0192|GPUREG_0192]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_0193|GPUREG_0193]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_0194|GPUREG_0194]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_0195|GPUREG_0195]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_0196|GPUREG_0196]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_0197|GPUREG_0197]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_0199|GPUREG_0199]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_019A|GPUREG_019A]]
|
|
|-
| 019B
| [[#GPUREG_019B|GPUREG_019B]]
|
|
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_01A0|GPUREG_01A0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_01A1|GPUREG_01A1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_01A2|GPUREG_01A2]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_01A3|GPUREG_01A3]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_01A4|GPUREG_01A4]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_01A5|GPUREG_01A5]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_01A6|GPUREG_01A6]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_01A7|GPUREG_01A7]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_01A9|GPUREG_01A9]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_01AA|GPUREG_01AA]]
|
|
|-
| 01AB
| [[#GPUREG_01AB|GPUREG_01AB]]
|
|
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_01B0|GPUREG_01B0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_01B1|GPUREG_01B1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_01B2|GPUREG_01B2]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_01B3|GPUREG_01B3]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_01B4|GPUREG_01B4]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_01B5|GPUREG_01B5]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_01B6|GPUREG_01B6]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_01B7|GPUREG_01B7]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_01B9|GPUREG_01B9]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_01BA|GPUREG_01BA]]
|
|
|-
| 01BB
| [[#GPUREG_01BB|GPUREG_01BB]]
|
|
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_01C0|GPUREG_01C0]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_01C2|GPUREG_01C2]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_01C3|GPUREG_01C3]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_01C4|GPUREG_01C4]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_01C5|GPUREG_01C5]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_01C6|GPUREG_01C6]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_01C8|GPUREG_01C8]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_01C9|GPUREG_01C9]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_01CA|GPUREG_01CA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_01CB|GPUREG_01CB]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_01CC|GPUREG_01CC]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_01CD|GPUREG_01CD]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA8
|-
| 01CE
| [[#GPUREG_01CE|GPUREG_01CE]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_01CF|GPUREG_01CF]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_01D0|GPUREG_01D0]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_01D1|GPUREG_01D1]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_01D2|GPUREG_01D2]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_01D9|GPUREG_01D9]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFER0_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFER0_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFER0_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFER1_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFER1_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFER1_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFER2_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFER2_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFER2_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFER3_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFER3_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFER3_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFER4_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFER4_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFER4_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFER5_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFER5_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFER5_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFER6_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFER6_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFER6_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFER7_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFER7_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFER7_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFER8_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFER8_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFER8_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFER9_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFER9_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFER9_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFER10_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFER10_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFER10_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFER11_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFER11_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFER11_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_022D|GPUREG_022D]]
|
|
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_0231|GPUREG_0231]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_0242|GPUREG_0242]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_0244|GPUREG_0244]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_0245|GPUREG_0245]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_024A|GPUREG_024A]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_0251|GPUREG_0251]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_0252|GPUREG_0252]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_0253|GPUREG_0253]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_0254|GPUREG_0254]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_GSH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_GSH_INTUNIFORM_I0|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_GSH_INTUNIFORM_I1|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_GSH_INTUNIFORM_I2|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_GSH_INTUNIFORM_I3|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_GSH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_GSH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_GSH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0292
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0293
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0294
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0295
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0296
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0297
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0298
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA8
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_GSH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_GSH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_VSH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_VSH_INTUNIFORM_I0|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_VSH_INTUNIFORM_I1|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_VSH_INTUNIFORM_I2|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_VSH_INTUNIFORM_I3|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_VSH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_VSH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C2
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C3
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C4
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C5
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C6
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C7
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C8
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA8
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_VSH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_VSH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

== Texturing registers ==

== Framebuffer registers ==

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_DEPTHBUFFER_FORMAT ===

The format the current depth buffer should be written into. Following values are possible:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 1
| ?? seems to freeze the GPU
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil (stencil is within bit 24-31)
|}

=== GPUREG_COLORBUFFER_FORMAT ===

Describes the format of the current color buffer used for 3D rendering.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?)
|-
| 16-23
| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].

Color components are laid out in reverse byte order, with the most significant bits used first.
|}

== Fragment lighting registers ==

=== GPUREG_01C4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Disable bit for frag light source 0 shadows
|-
| 1
| Disable bit for frag light source 1 shadows
|-
| 2
| Disable bit for frag light source 2 shadows
|-
| 3
| Disable bit for frag light source 3 shadows
|-
| 4
| Disable bit for frag light source 4 shadows
|-
| 5
| Disable bit for frag light source 5 shadows
|-
| 6
| Disable bit for frag light source 6 shadows
|-
| 7
| Disable bit for frag light source 7 shadows
|-
| 8
| Disable bit for frag light source 0 spot
|-
| 9
| Disable bit for frag light source 1 spot
|-
| 10
| Disable bit for frag light source 2 spot
|-
| 11
| Disable bit for frag light source 3 spot
|-
| 12
| Disable bit for frag light source 4 spot
|-
| 13
| Disable bit for frag light source 5 spot
|-
| 14
| Disable bit for frag light source 6 spot
|-
| 15
| Disable bit for frag light source 7 spot
|-
| 24
| Disable bit for frag light source 0 distance attenuation
|-
| 25
| Disable bit for frag light source 1 distance attenuation
|-
| 26
| Disable bit for frag light source 2 distance attenuation
|-
| 27
| Disable bit for frag light source 3 distance attenuation
|-
| 28
| Disable bit for frag light source 4 distance attenuation
|-
| 29
| Disable bit for frag light source 5 distance attenuation
|-
| 30
| Disable bit for frag light source 6 distance attenuation
|-
| 31
| Disable bit for frag light source 7 distance attenuation
|}

== Geometry pipeline registers ==

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
|-
| 8
| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''
|-
| 9-15
| No effect.
|-
| 16-23
| Unknown.
|-
| 24-31
| Unknown. Often set to 0.
|}

This register configures the geometry stage of the GPU pipeline.

=== GPUREG_FIXEDATTRIB_INDEX ===

See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline.
|}

=== GPUREG_FIXEDATTRIB_DATA ===

Accepts a packed 4-tuple of float24 values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].

If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]], but most games seem to write to it before every draw call.
|}

== Geometry shader registers ==

=== GPUREG_GSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the geometry shader unit's boolean registers.

=== GPUREG_GSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i0.w (u8, 0-255)
|}

This register is used to set the geometry shader's i0 integer register.

=== GPUREG_GSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i1.w (u8, 0-255)
|}

This register is used to set the geometry shader's i1 integer register.

=== GPUREG_GSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i2.w (u8, 0-255)
|}

This register is used to set the geometry shader's i2 integer register.

=== GPUREG_GSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i3.w (u8, 0-255)
|}

This register is used to set the geometry shader's i3 integer register.

=== GPUREG_GSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 8 for geometry shaders.
|}

This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.

=== GPUREG_GSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Geometry shader unit entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 8th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 16th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_GSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|}

This register toggles the geometry shader unit's output registers.

=== GPUREG_GSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.

=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_GSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_GSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target geometry shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_GSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader instruction data.
|}

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_GSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target geometry shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.

=== GPUREG_GSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader operand descriptor data.
|}

This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

== Vertex shader registers ==

=== GPUREG_VSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of vertex shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of vertex shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of vertex shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of vertex shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of vertex shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of vertex shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of vertex shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of vertex shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the vertex shader unit's boolean registers.

=== GPUREG_VSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i0.w (u8, 0-255)
|}

This register is used to set the vertex shader's i0 integer register.

=== GPUREG_VSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i1.w (u8, 0-255)
|}

This register is used to set the vertex shader's i1 integer register.

=== GPUREG_VSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i2.w (u8, 0-255)
|}

This register is used to set the vertex shader's i2 integer register.

=== GPUREG_VSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i3.w (u8, 0-255)
|}

This register is used to set the vertex shader's i3 integer register.

=== GPUREG_VSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 0xA for vertex shaders.
|}

This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.

=== GPUREG_VSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Vertex shader entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 8th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 16th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_VSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|-
| 7
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
|-
| 8
| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
|-
| 9
| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
|-
| 10
| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
|-
| 11
| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
|-
| 12
| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
|-
| 13
| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
|-
| 14
| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
|-
| 15
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
|}

This register toggles the vertex shader units' output registers.

=== GPUREG_VSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.

=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_VSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_VSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target vertex shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_VSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader instruction data.
|}

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_VSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target vertex shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.

=== GPUREG_VSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader operand descriptor data.
|}

This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

[[Category:GPU]]

GPU/Internal Registers

2015-09-07T03:05:52Z

Yuriks: /* Framebuffer registers (0x100-0x13F) */

[[Category:GFX]]
(this page is hugely WIP)

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_0047|GPUREG_0047]]
|?
|PICA_REG_FRAG_OP_CLIP
|-
| 0048
| [[#GPUREG_0048|GPUREG_0048]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_0049|GPUREG_0049]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_004A|GPUREG_004A]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_004B|GPUREG_004B]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_O0|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_O1|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_O2|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_O3|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_O4|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_O5|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_O6|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_0061|GPUREG_0061]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_0062|GPUREG_0062]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_0063|GPUREG_0063]]
|
|
|-
| 0064
| [[#GPUREG_0064|GPUREG_0064]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_006A|GPUREG_006A]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_006D|GPUREG_006D]]
|?
|PICA_REG_FRAG_OP_WSCALE
|-
| 006E
| [[#GPUREG_FRAMEBUFFER_DIM2|GPUREG_FRAMEBUFFER_DIM2]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_006F|GPUREG_006F]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_ENABLE|GPUREG_TEXUNIT_ENABLE]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNIT0_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNIT0_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNIT0_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_0084|GPUREG_0084]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNIT0_LOC|GPUREG_TEXUNIT0_LOC]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_0086|GPUREG_0086]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_0087|GPUREG_0087]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_0088|GPUREG_0088]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_0089|GPUREG_0089]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_008A|GPUREG_008A]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_008B|GPUREG_008B]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNIT0_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_008F|GPUREG_008F]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNIT1_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNIT1_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNIT1_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_0094|GPUREG_0094]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNIT1_LOC|GPUREG_TEXUNIT1_LOC]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNIT1_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNIT2_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNIT2_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNIT2_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_009C|GPUREG_009C]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNIT2_LOC|GPUREG_TEXUNIT2_LOC]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNIT2_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_00A8|GPUREG_00A8]]
|?
|PICA_REG_TEXTURE3_PROTEX0
|-
| 00A9
| [[#GPUREG_00A9|GPUREG_00A9]]
|?
|PICA_REG_TEXTURE3_PROTEX1
|-
| 00AA
| [[#GPUREG_00AA|GPUREG_00AA]]
|?
|PICA_REG_TEXTURE3_PROTEX2
|-
| 00AB
| [[#GPUREG_00AB|GPUREG_00AB]]
|?
|PICA_REG_TEXTURE3_PROTEX3
|-
| 00AC
| [[#GPUREG_00AC|GPUREG_00AC]]
|?
|PICA_REG_TEXTURE3_PROTEX4
|-
| 00AD
| [[#GPUREG_00AD|GPUREG_00AD]]
|?
|PICA_REG_TEXTURE3_PROTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_00AF|GPUREG_00AF]]
|?
|PICA_REG_PROTEX_LUT
|-
| 00B0
| [[#GPUREG_00B0|GPUREG_00B0]]
| ?
|PICA_REG_PROTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_00B1|GPUREG_00B1]]
| ?
|PICA_REG_PROTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_00B2|GPUREG_00B2]]
| ?
|PICA_REG_PROTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_00B3|GPUREG_00B3]]
| ?
|PICA_REG_PROTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_00B4|GPUREG_00B4]]
| ?
|PICA_REG_PROTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_00B5|GPUREG_00B5]]
| ?
|PICA_REG_PROTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_00B6|GPUREG_00B6]]
| ?
|PICA_REG_PROTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_00B7|GPUREG_00B7]]
| ?
|PICA_REG_PROTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENV0_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENV0_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENV0_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENV0_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENV0_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENV1_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENV1_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENV1_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENV1_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENV1_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENV2_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENV2_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENV2_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENV2_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENV2_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENV3_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENV3_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENV3_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENV3_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENV3_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_00E1|GPUREG_00E1]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_00E4|GPUREG_00E4]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_00E5|GPUREG_00E5]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_00E6|GPUREG_00E6]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_00E8|GPUREG_00E8]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_00E9|GPUREG_00E9]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_00EA|GPUREG_00EA]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_00EB|GPUREG_00EB]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_00EC|GPUREG_00EC]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_00ED|GPUREG_00ED]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_00EE|GPUREG_00EE]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_00EF|GPUREG_00EF]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENV4_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENV4_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENV4_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENV4_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENV4_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENV5_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENV5_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENV5_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENV5_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENV5_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_BLEND_ENABLE|GPUREG_BLEND_ENABLE]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_CONFIG|GPUREG_BLEND_CONFIG]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGICOP_CONFIG|GPUREG_LOGICOP_CONFIG]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_ALPHATEST_CONFIG|GPUREG_ALPHATEST_CONFIG]]
|
|PICA_REG_FRAG_OP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_ACTION|GPUREG_STENCIL_ACTION]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTHTEST_CONFIG|GPUREG_DEPTHTEST_CONFIG]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_0118|GPUREG_0118]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_011B|GPUREG_011B]]
|?
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_0120|GPUREG_0120]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_0121|GPUREG_0121]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_0122|GPUREG_0122]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_0123|GPUREG_0123]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_0124|GPUREG_0124]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_0126|GPUREG_0126]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_0130|GPUREG_0130]]
|?
|PICA_REG_FRAG_OP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_0140|GPUREG_0140]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_0141|GPUREG_0141]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_0142|GPUREG_0142]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_0143|GPUREG_0143]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_0144|GPUREG_0144]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_0145|GPUREG_0145]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_0146|GPUREG_0146]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_0147|GPUREG_0147]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_0149|GPUREG_0149]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_014A|GPUREG_014A]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_014B|GPUREG_014B]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_0150|GPUREG_0150]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_0151|GPUREG_0151]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_0152|GPUREG_0152]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_0153|GPUREG_0153]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_0154|GPUREG_0154]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_0155|GPUREG_0155]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_0156|GPUREG_0156]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_0157|GPUREG_0157]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_0159|GPUREG_0159]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_015A|GPUREG_015A]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_015B|GPUREG_015B]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_0160|GPUREG_0160]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_0161|GPUREG_0161]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_0162|GPUREG_0162]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_0163|GPUREG_0163]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_0164|GPUREG_0164]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_0165|GPUREG_0165]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_0166|GPUREG_0166]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_0167|GPUREG_0167]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_0169|GPUREG_0169]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_016A|GPUREG_016A]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_016B|GPUREG_016B]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_0170|GPUREG_0170]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_0171|GPUREG_0171]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_0172|GPUREG_0172]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_0173|GPUREG_0173]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_0174|GPUREG_0174]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_0175|GPUREG_0175]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_0176|GPUREG_0176]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_0177|GPUREG_0177]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_0179|GPUREG_0179]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_017A|GPUREG_017A]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_017B|GPUREG_017B]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_0180|GPUREG_0180]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_0181|GPUREG_0181]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_0182|GPUREG_0182]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_0183|GPUREG_0183]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_0184|GPUREG_0184]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_0185|GPUREG_0185]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_0186|GPUREG_0186]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_0187|GPUREG_0187]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_0189|GPUREG_0189]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_018A|GPUREG_018A]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_018B|GPUREG_018B]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_0190|GPUREG_0190]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_0191|GPUREG_0191]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_0192|GPUREG_0192]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_0193|GPUREG_0193]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_0194|GPUREG_0194]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_0195|GPUREG_0195]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_0196|GPUREG_0196]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_0197|GPUREG_0197]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_0199|GPUREG_0199]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_019A|GPUREG_019A]]
|
|
|-
| 019B
| [[#GPUREG_019B|GPUREG_019B]]
|
|
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_01A0|GPUREG_01A0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_01A1|GPUREG_01A1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_01A2|GPUREG_01A2]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_01A3|GPUREG_01A3]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_01A4|GPUREG_01A4]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_01A5|GPUREG_01A5]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_01A6|GPUREG_01A6]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_01A7|GPUREG_01A7]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_01A9|GPUREG_01A9]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_01AA|GPUREG_01AA]]
|
|
|-
| 01AB
| [[#GPUREG_01AB|GPUREG_01AB]]
|
|
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_01B0|GPUREG_01B0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_01B1|GPUREG_01B1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_01B2|GPUREG_01B2]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_01B3|GPUREG_01B3]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_01B4|GPUREG_01B4]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_01B5|GPUREG_01B5]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_01B6|GPUREG_01B6]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_01B7|GPUREG_01B7]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_01B9|GPUREG_01B9]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_01BA|GPUREG_01BA]]
|
|
|-
| 01BB
| [[#GPUREG_01BB|GPUREG_01BB]]
|
|
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_01C0|GPUREG_01C0]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_01C2|GPUREG_01C2]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_01C3|GPUREG_01C3]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_01C4|GPUREG_01C4]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_01C5|GPUREG_01C5]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_01C6|GPUREG_01C6]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_01C8|GPUREG_01C8]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_01C9|GPUREG_01C9]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_01CA|GPUREG_01CA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_01CB|GPUREG_01CB]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_01CC|GPUREG_01CC]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_01CD|GPUREG_01CD]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA8
|-
| 01CE
| [[#GPUREG_01CE|GPUREG_01CE]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_01CF|GPUREG_01CF]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_01D0|GPUREG_01D0]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_01D1|GPUREG_01D1]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_01D2|GPUREG_01D2]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_01D9|GPUREG_01D9]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFER0_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFER0_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFER0_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFER1_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFER1_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFER1_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFER2_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFER2_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFER2_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFER3_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFER3_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFER3_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFER4_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFER4_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFER4_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFER5_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFER5_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFER5_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFER6_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFER6_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFER6_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFER7_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFER7_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFER7_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFER8_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFER8_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFER8_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFER9_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFER9_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFER9_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFER10_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFER10_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFER10_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFER11_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFER11_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFER11_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_022D|GPUREG_022D]]
|
|
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_0231|GPUREG_0231]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_0242|GPUREG_0242]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_0244|GPUREG_0244]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_0245|GPUREG_0245]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_024A|GPUREG_024A]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_0251|GPUREG_0251]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_0252|GPUREG_0252]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_0253|GPUREG_0253]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_0254|GPUREG_0254]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_GSH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_GSH_INTUNIFORM_I0|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_GSH_INTUNIFORM_I1|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_GSH_INTUNIFORM_I2|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_GSH_INTUNIFORM_I3|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_GSH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_GSH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_GSH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0292
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0293
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0294
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0295
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0296
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0297
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0298
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA8
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_GSH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_GSH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_VSH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_VSH_INTUNIFORM_I0|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_VSH_INTUNIFORM_I1|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_VSH_INTUNIFORM_I2|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_VSH_INTUNIFORM_I3|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_VSH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_VSH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C2
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C3
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C4
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C5
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C6
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C7
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C8
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA8
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_VSH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_VSH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

== Texturing registers ==

== Framebuffer registers ==

=== GPUREG_DEPTHBUFFER_FORMAT ===

The format the current depth buffer should be written into. Following values are possible:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 1
| ?? seems to freeze the GPU
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil (stencil is within bit 24-31)
|}

=== GPUREG_COLORBUFFER_FORMAT ===

Describes the format of the current color buffer used for 3D rendering.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?)
|-
| 16-23
| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].

Color components are laid out in reverse byte order, with the most significant bits used first.
|}

== Fragment lighting registers ==

=== GPUREG_01C4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Disable bit for frag light source 0 shadows
|-
| 1
| Disable bit for frag light source 1 shadows
|-
| 2
| Disable bit for frag light source 2 shadows
|-
| 3
| Disable bit for frag light source 3 shadows
|-
| 4
| Disable bit for frag light source 4 shadows
|-
| 5
| Disable bit for frag light source 5 shadows
|-
| 6
| Disable bit for frag light source 6 shadows
|-
| 7
| Disable bit for frag light source 7 shadows
|-
| 8
| Disable bit for frag light source 0 spot
|-
| 9
| Disable bit for frag light source 1 spot
|-
| 10
| Disable bit for frag light source 2 spot
|-
| 11
| Disable bit for frag light source 3 spot
|-
| 12
| Disable bit for frag light source 4 spot
|-
| 13
| Disable bit for frag light source 5 spot
|-
| 14
| Disable bit for frag light source 6 spot
|-
| 15
| Disable bit for frag light source 7 spot
|-
| 24
| Disable bit for frag light source 0 distance attenuation
|-
| 25
| Disable bit for frag light source 1 distance attenuation
|-
| 26
| Disable bit for frag light source 2 distance attenuation
|-
| 27
| Disable bit for frag light source 3 distance attenuation
|-
| 28
| Disable bit for frag light source 4 distance attenuation
|-
| 29
| Disable bit for frag light source 5 distance attenuation
|-
| 30
| Disable bit for frag light source 6 distance attenuation
|-
| 31
| Disable bit for frag light source 7 distance attenuation
|}

== Geometry pipeline registers ==

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
|-
| 8
| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''
|-
| 9-15
| No effect.
|-
| 16-23
| Unknown.
|-
| 24-31
| Unknown. Often set to 0.
|}

This register configures the geometry stage of the GPU pipeline.

=== GPUREG_FIXEDATTRIB_INDEX ===

See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline.
|}

=== GPUREG_FIXEDATTRIB_DATA ===

Accepts a packed 4-tuple of float24 values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].

If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]], but most games seem to write to it before every draw call.
|}

== Geometry shader registers ==

=== GPUREG_GSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the geometry shader unit's boolean registers.

=== GPUREG_GSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i0.w (u8, 0-255)
|}

This register is used to set the geometry shader's i0 integer register.

=== GPUREG_GSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i1.w (u8, 0-255)
|}

This register is used to set the geometry shader's i1 integer register.

=== GPUREG_GSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i2.w (u8, 0-255)
|}

This register is used to set the geometry shader's i2 integer register.

=== GPUREG_GSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i3.w (u8, 0-255)
|}

This register is used to set the geometry shader's i3 integer register.

=== GPUREG_GSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 8 for geometry shaders.
|}

This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.

=== GPUREG_GSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Geometry shader unit entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 8th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 16th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_GSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|}

This register toggles the geometry shader unit's output registers.

=== GPUREG_GSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.

=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_GSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_GSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target geometry shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_GSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader instruction data.
|}

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_GSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target geometry shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.

=== GPUREG_GSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader operand descriptor data.
|}

This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

== Vertex shader registers ==

=== GPUREG_VSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of vertex shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of vertex shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of vertex shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of vertex shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of vertex shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of vertex shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of vertex shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of vertex shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the vertex shader unit's boolean registers.

=== GPUREG_VSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i0.w (u8, 0-255)
|}

This register is used to set the vertex shader's i0 integer register.

=== GPUREG_VSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i1.w (u8, 0-255)
|}

This register is used to set the vertex shader's i1 integer register.

=== GPUREG_VSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i2.w (u8, 0-255)
|}

This register is used to set the vertex shader's i2 integer register.

=== GPUREG_VSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i3.w (u8, 0-255)
|}

This register is used to set the vertex shader's i3 integer register.

=== GPUREG_VSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 0xA for vertex shaders.
|}

This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.

=== GPUREG_VSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Vertex shader entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 8th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 16th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_VSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|-
| 7
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
|-
| 8
| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
|-
| 9
| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
|-
| 10
| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
|-
| 11
| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
|-
| 12
| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
|-
| 13
| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
|-
| 14
| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
|-
| 15
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
|}

This register toggles the vertex shader units' output registers.

=== GPUREG_VSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.

=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_VSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_VSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target vertex shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_VSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader instruction data.
|}

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_VSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target vertex shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.

=== GPUREG_VSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader operand descriptor data.
|}

This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

[[Category:GPU]]

GPU/Internal Registers

2015-09-07T03:05:30Z

Yuriks: /* Framebuffer registers (0x100-0x13F) */ Add names to regs 0x111 and 0x110

[[Category:GFX]]
(this page is hugely WIP)

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_0047|GPUREG_0047]]
|?
|PICA_REG_FRAG_OP_CLIP
|-
| 0048
| [[#GPUREG_0048|GPUREG_0048]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_0049|GPUREG_0049]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_004A|GPUREG_004A]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_004B|GPUREG_004B]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_O0|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_O1|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_O2|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_O3|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_O4|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_O5|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_O6|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_0061|GPUREG_0061]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_0062|GPUREG_0062]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_0063|GPUREG_0063]]
|
|
|-
| 0064
| [[#GPUREG_0064|GPUREG_0064]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_006A|GPUREG_006A]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_006D|GPUREG_006D]]
|?
|PICA_REG_FRAG_OP_WSCALE
|-
| 006E
| [[#GPUREG_FRAMEBUFFER_DIM2|GPUREG_FRAMEBUFFER_DIM2]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_006F|GPUREG_006F]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_ENABLE|GPUREG_TEXUNIT_ENABLE]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNIT0_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNIT0_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNIT0_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_0084|GPUREG_0084]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNIT0_LOC|GPUREG_TEXUNIT0_LOC]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_0086|GPUREG_0086]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_0087|GPUREG_0087]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_0088|GPUREG_0088]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_0089|GPUREG_0089]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_008A|GPUREG_008A]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_008B|GPUREG_008B]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNIT0_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_008F|GPUREG_008F]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNIT1_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNIT1_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNIT1_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_0094|GPUREG_0094]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNIT1_LOC|GPUREG_TEXUNIT1_LOC]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNIT1_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNIT2_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNIT2_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNIT2_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_009C|GPUREG_009C]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNIT2_LOC|GPUREG_TEXUNIT2_LOC]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNIT2_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_00A8|GPUREG_00A8]]
|?
|PICA_REG_TEXTURE3_PROTEX0
|-
| 00A9
| [[#GPUREG_00A9|GPUREG_00A9]]
|?
|PICA_REG_TEXTURE3_PROTEX1
|-
| 00AA
| [[#GPUREG_00AA|GPUREG_00AA]]
|?
|PICA_REG_TEXTURE3_PROTEX2
|-
| 00AB
| [[#GPUREG_00AB|GPUREG_00AB]]
|?
|PICA_REG_TEXTURE3_PROTEX3
|-
| 00AC
| [[#GPUREG_00AC|GPUREG_00AC]]
|?
|PICA_REG_TEXTURE3_PROTEX4
|-
| 00AD
| [[#GPUREG_00AD|GPUREG_00AD]]
|?
|PICA_REG_TEXTURE3_PROTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_00AF|GPUREG_00AF]]
|?
|PICA_REG_PROTEX_LUT
|-
| 00B0
| [[#GPUREG_00B0|GPUREG_00B0]]
| ?
|PICA_REG_PROTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_00B1|GPUREG_00B1]]
| ?
|PICA_REG_PROTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_00B2|GPUREG_00B2]]
| ?
|PICA_REG_PROTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_00B3|GPUREG_00B3]]
| ?
|PICA_REG_PROTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_00B4|GPUREG_00B4]]
| ?
|PICA_REG_PROTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_00B5|GPUREG_00B5]]
| ?
|PICA_REG_PROTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_00B6|GPUREG_00B6]]
| ?
|PICA_REG_PROTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_00B7|GPUREG_00B7]]
| ?
|PICA_REG_PROTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENV0_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENV0_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENV0_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENV0_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENV0_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENV1_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENV1_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENV1_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENV1_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENV1_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENV2_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENV2_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENV2_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENV2_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENV2_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENV3_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENV3_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENV3_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENV3_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENV3_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_00E1|GPUREG_00E1]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_00E4|GPUREG_00E4]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_00E5|GPUREG_00E5]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_00E6|GPUREG_00E6]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_00E8|GPUREG_00E8]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_00E9|GPUREG_00E9]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_00EA|GPUREG_00EA]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_00EB|GPUREG_00EB]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_00EC|GPUREG_00EC]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_00ED|GPUREG_00ED]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_00EE|GPUREG_00EE]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_00EF|GPUREG_00EF]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENV4_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENV4_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENV4_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENV4_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENV4_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENV5_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENV5_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENV5_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENV5_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENV5_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_BLEND_ENABLE|GPUREG_BLEND_ENABLE]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_CONFIG|GPUREG_BLEND_CONFIG]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGICOP_CONFIG|GPUREG_LOGICOP_CONFIG]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_ALPHATEST_CONFIG|GPUREG_ALPHATEST_CONFIG]]
|
|PICA_REG_FRAG_OP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_ACTION|GPUREG_STENCIL_ACTION]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTHTEST_CONFIG|GPUREG_DEPTHTEST_CONFIG]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|?
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|?
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_0118|GPUREG_0118]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_011B|GPUREG_011B]]
|?
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_0120|GPUREG_0120]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_0121|GPUREG_0121]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_0122|GPUREG_0122]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_0123|GPUREG_0123]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_0124|GPUREG_0124]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_0126|GPUREG_0126]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_0130|GPUREG_0130]]
|?
|PICA_REG_FRAG_OP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_0140|GPUREG_0140]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_0141|GPUREG_0141]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_0142|GPUREG_0142]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_0143|GPUREG_0143]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_0144|GPUREG_0144]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_0145|GPUREG_0145]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_0146|GPUREG_0146]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_0147|GPUREG_0147]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_0149|GPUREG_0149]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_014A|GPUREG_014A]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_014B|GPUREG_014B]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_0150|GPUREG_0150]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_0151|GPUREG_0151]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_0152|GPUREG_0152]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_0153|GPUREG_0153]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_0154|GPUREG_0154]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_0155|GPUREG_0155]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_0156|GPUREG_0156]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_0157|GPUREG_0157]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_0159|GPUREG_0159]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_015A|GPUREG_015A]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_015B|GPUREG_015B]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_0160|GPUREG_0160]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_0161|GPUREG_0161]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_0162|GPUREG_0162]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_0163|GPUREG_0163]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_0164|GPUREG_0164]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_0165|GPUREG_0165]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_0166|GPUREG_0166]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_0167|GPUREG_0167]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_0169|GPUREG_0169]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_016A|GPUREG_016A]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_016B|GPUREG_016B]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_0170|GPUREG_0170]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_0171|GPUREG_0171]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_0172|GPUREG_0172]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_0173|GPUREG_0173]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_0174|GPUREG_0174]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_0175|GPUREG_0175]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_0176|GPUREG_0176]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_0177|GPUREG_0177]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_0179|GPUREG_0179]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_017A|GPUREG_017A]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_017B|GPUREG_017B]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_0180|GPUREG_0180]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_0181|GPUREG_0181]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_0182|GPUREG_0182]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_0183|GPUREG_0183]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_0184|GPUREG_0184]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_0185|GPUREG_0185]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_0186|GPUREG_0186]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_0187|GPUREG_0187]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_0189|GPUREG_0189]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_018A|GPUREG_018A]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_018B|GPUREG_018B]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_0190|GPUREG_0190]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_0191|GPUREG_0191]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_0192|GPUREG_0192]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_0193|GPUREG_0193]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_0194|GPUREG_0194]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_0195|GPUREG_0195]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_0196|GPUREG_0196]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_0197|GPUREG_0197]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_0199|GPUREG_0199]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_019A|GPUREG_019A]]
|
|
|-
| 019B
| [[#GPUREG_019B|GPUREG_019B]]
|
|
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_01A0|GPUREG_01A0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_01A1|GPUREG_01A1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_01A2|GPUREG_01A2]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_01A3|GPUREG_01A3]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_01A4|GPUREG_01A4]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_01A5|GPUREG_01A5]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_01A6|GPUREG_01A6]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_01A7|GPUREG_01A7]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_01A9|GPUREG_01A9]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_01AA|GPUREG_01AA]]
|
|
|-
| 01AB
| [[#GPUREG_01AB|GPUREG_01AB]]
|
|
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_01B0|GPUREG_01B0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_01B1|GPUREG_01B1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_01B2|GPUREG_01B2]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_01B3|GPUREG_01B3]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_01B4|GPUREG_01B4]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_01B5|GPUREG_01B5]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_01B6|GPUREG_01B6]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_01B7|GPUREG_01B7]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_01B9|GPUREG_01B9]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_01BA|GPUREG_01BA]]
|
|
|-
| 01BB
| [[#GPUREG_01BB|GPUREG_01BB]]
|
|
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_01C0|GPUREG_01C0]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_01C2|GPUREG_01C2]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_01C3|GPUREG_01C3]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_01C4|GPUREG_01C4]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_01C5|GPUREG_01C5]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_01C6|GPUREG_01C6]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_01C8|GPUREG_01C8]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_01C9|GPUREG_01C9]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_01CA|GPUREG_01CA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_01CB|GPUREG_01CB]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_01CC|GPUREG_01CC]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_01CD|GPUREG_01CD]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA8
|-
| 01CE
| [[#GPUREG_01CE|GPUREG_01CE]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_01CF|GPUREG_01CF]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_01D0|GPUREG_01D0]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_01D1|GPUREG_01D1]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_01D2|GPUREG_01D2]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_01D9|GPUREG_01D9]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFER0_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFER0_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFER0_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFER1_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFER1_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFER1_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFER2_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFER2_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFER2_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFER3_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFER3_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFER3_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFER4_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFER4_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFER4_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFER5_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFER5_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFER5_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFER6_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFER6_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFER6_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFER7_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFER7_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFER7_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFER8_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFER8_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFER8_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFER9_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFER9_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFER9_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFER10_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFER10_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFER10_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFER11_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFER11_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFER11_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_022D|GPUREG_022D]]
|
|
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_0231|GPUREG_0231]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_0242|GPUREG_0242]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_0244|GPUREG_0244]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_0245|GPUREG_0245]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_024A|GPUREG_024A]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_0251|GPUREG_0251]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_0252|GPUREG_0252]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_0253|GPUREG_0253]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_0254|GPUREG_0254]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_GSH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_GSH_INTUNIFORM_I0|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_GSH_INTUNIFORM_I1|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_GSH_INTUNIFORM_I2|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_GSH_INTUNIFORM_I3|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_GSH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_GSH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_GSH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0292
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0293
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0294
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0295
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0296
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0297
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0298
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA8
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_GSH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_GSH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_VSH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_VSH_INTUNIFORM_I0|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_VSH_INTUNIFORM_I1|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_VSH_INTUNIFORM_I2|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_VSH_INTUNIFORM_I3|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_VSH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_VSH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C2
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C3
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C4
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C5
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C6
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C7
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C8
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA8
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_VSH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_VSH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

== Texturing registers ==

== Framebuffer registers ==

=== GPUREG_DEPTHBUFFER_FORMAT ===

The format the current depth buffer should be written into. Following values are possible:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 1
| ?? seems to freeze the GPU
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil (stencil is within bit 24-31)
|}

=== GPUREG_COLORBUFFER_FORMAT ===

Describes the format of the current color buffer used for 3D rendering.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?)
|-
| 16-23
| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].

Color components are laid out in reverse byte order, with the most significant bits used first.
|}

== Fragment lighting registers ==

=== GPUREG_01C4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Disable bit for frag light source 0 shadows
|-
| 1
| Disable bit for frag light source 1 shadows
|-
| 2
| Disable bit for frag light source 2 shadows
|-
| 3
| Disable bit for frag light source 3 shadows
|-
| 4
| Disable bit for frag light source 4 shadows
|-
| 5
| Disable bit for frag light source 5 shadows
|-
| 6
| Disable bit for frag light source 6 shadows
|-
| 7
| Disable bit for frag light source 7 shadows
|-
| 8
| Disable bit for frag light source 0 spot
|-
| 9
| Disable bit for frag light source 1 spot
|-
| 10
| Disable bit for frag light source 2 spot
|-
| 11
| Disable bit for frag light source 3 spot
|-
| 12
| Disable bit for frag light source 4 spot
|-
| 13
| Disable bit for frag light source 5 spot
|-
| 14
| Disable bit for frag light source 6 spot
|-
| 15
| Disable bit for frag light source 7 spot
|-
| 24
| Disable bit for frag light source 0 distance attenuation
|-
| 25
| Disable bit for frag light source 1 distance attenuation
|-
| 26
| Disable bit for frag light source 2 distance attenuation
|-
| 27
| Disable bit for frag light source 3 distance attenuation
|-
| 28
| Disable bit for frag light source 4 distance attenuation
|-
| 29
| Disable bit for frag light source 5 distance attenuation
|-
| 30
| Disable bit for frag light source 6 distance attenuation
|-
| 31
| Disable bit for frag light source 7 distance attenuation
|}

== Geometry pipeline registers ==

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
|-
| 8
| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''
|-
| 9-15
| No effect.
|-
| 16-23
| Unknown.
|-
| 24-31
| Unknown. Often set to 0.
|}

This register configures the geometry stage of the GPU pipeline.

=== GPUREG_FIXEDATTRIB_INDEX ===

See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline.
|}

=== GPUREG_FIXEDATTRIB_DATA ===

Accepts a packed 4-tuple of float24 values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].

If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]], but most games seem to write to it before every draw call.
|}

== Geometry shader registers ==

=== GPUREG_GSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the geometry shader unit's boolean registers.

=== GPUREG_GSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i0.w (u8, 0-255)
|}

This register is used to set the geometry shader's i0 integer register.

=== GPUREG_GSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i1.w (u8, 0-255)
|}

This register is used to set the geometry shader's i1 integer register.

=== GPUREG_GSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i2.w (u8, 0-255)
|}

This register is used to set the geometry shader's i2 integer register.

=== GPUREG_GSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i3.w (u8, 0-255)
|}

This register is used to set the geometry shader's i3 integer register.

=== GPUREG_GSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 8 for geometry shaders.
|}

This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.

=== GPUREG_GSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Geometry shader unit entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 8th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 16th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_GSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|}

This register toggles the geometry shader unit's output registers.

=== GPUREG_GSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.

=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_GSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_GSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target geometry shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_GSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader instruction data.
|}

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_GSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target geometry shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.

=== GPUREG_GSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader operand descriptor data.
|}

This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

== Vertex shader registers ==

=== GPUREG_VSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of vertex shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of vertex shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of vertex shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of vertex shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of vertex shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of vertex shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of vertex shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of vertex shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the vertex shader unit's boolean registers.

=== GPUREG_VSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i0.w (u8, 0-255)
|}

This register is used to set the vertex shader's i0 integer register.

=== GPUREG_VSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i1.w (u8, 0-255)
|}

This register is used to set the vertex shader's i1 integer register.

=== GPUREG_VSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i2.w (u8, 0-255)
|}

This register is used to set the vertex shader's i2 integer register.

=== GPUREG_VSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i3.w (u8, 0-255)
|}

This register is used to set the vertex shader's i3 integer register.

=== GPUREG_VSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 0xA for vertex shaders.
|}

This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.

=== GPUREG_VSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Vertex shader entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 8th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 16th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_VSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|-
| 7
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
|-
| 8
| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
|-
| 9
| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
|-
| 10
| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
|-
| 11
| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
|-
| 12
| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
|-
| 13
| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
|-
| 14
| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
|-
| 15
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
|}

This register toggles the vertex shader units' output registers.

=== GPUREG_VSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.

=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_VSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_VSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target vertex shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_VSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader instruction data.
|}

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_VSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target vertex shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.

=== GPUREG_VSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader operand descriptor data.
|}

This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

[[Category:GPU]]

GPU/Internal Registers

2015-09-07T01:09:06Z

Yuriks: /* GPUREG_GEOSTAGE_CONFIG */

[[Category:GFX]]
(this page is hugely WIP)

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_0047|GPUREG_0047]]
|?
|PICA_REG_FRAG_OP_CLIP
|-
| 0048
| [[#GPUREG_0048|GPUREG_0048]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_0049|GPUREG_0049]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_004A|GPUREG_004A]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_004B|GPUREG_004B]]
|?
|PICA_REG_FRAG_OP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAG_OP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_O0|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_O1|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_O2|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_O3|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_O4|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_O5|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_O6|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_0061|GPUREG_0061]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_0062|GPUREG_0062]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_0063|GPUREG_0063]]
|
|
|-
| 0064
| [[#GPUREG_0064|GPUREG_0064]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_006A|GPUREG_006A]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_006D|GPUREG_006D]]
|?
|PICA_REG_FRAG_OP_WSCALE
|-
| 006E
| [[#GPUREG_FRAMEBUFFER_DIM2|GPUREG_FRAMEBUFFER_DIM2]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_006F|GPUREG_006F]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_ENABLE|GPUREG_TEXUNIT_ENABLE]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNIT0_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNIT0_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNIT0_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_0084|GPUREG_0084]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNIT0_LOC|GPUREG_TEXUNIT0_LOC]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_0086|GPUREG_0086]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_0087|GPUREG_0087]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_0088|GPUREG_0088]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_0089|GPUREG_0089]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_008A|GPUREG_008A]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_008B|GPUREG_008B]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNIT0_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_008F|GPUREG_008F]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNIT1_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNIT1_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNIT1_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_0094|GPUREG_0094]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNIT1_LOC|GPUREG_TEXUNIT1_LOC]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNIT1_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNIT2_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNIT2_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNIT2_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_009C|GPUREG_009C]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNIT2_LOC|GPUREG_TEXUNIT2_LOC]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNIT2_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_00A8|GPUREG_00A8]]
|?
|PICA_REG_TEXTURE3_PROTEX0
|-
| 00A9
| [[#GPUREG_00A9|GPUREG_00A9]]
|?
|PICA_REG_TEXTURE3_PROTEX1
|-
| 00AA
| [[#GPUREG_00AA|GPUREG_00AA]]
|?
|PICA_REG_TEXTURE3_PROTEX2
|-
| 00AB
| [[#GPUREG_00AB|GPUREG_00AB]]
|?
|PICA_REG_TEXTURE3_PROTEX3
|-
| 00AC
| [[#GPUREG_00AC|GPUREG_00AC]]
|?
|PICA_REG_TEXTURE3_PROTEX4
|-
| 00AD
| [[#GPUREG_00AD|GPUREG_00AD]]
|?
|PICA_REG_TEXTURE3_PROTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_00AF|GPUREG_00AF]]
|?
|PICA_REG_PROTEX_LUT
|-
| 00B0
| [[#GPUREG_00B0|GPUREG_00B0]]
| ?
|PICA_REG_PROTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_00B1|GPUREG_00B1]]
| ?
|PICA_REG_PROTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_00B2|GPUREG_00B2]]
| ?
|PICA_REG_PROTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_00B3|GPUREG_00B3]]
| ?
|PICA_REG_PROTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_00B4|GPUREG_00B4]]
| ?
|PICA_REG_PROTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_00B5|GPUREG_00B5]]
| ?
|PICA_REG_PROTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_00B6|GPUREG_00B6]]
| ?
|PICA_REG_PROTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_00B7|GPUREG_00B7]]
| ?
|PICA_REG_PROTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENV0_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENV0_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENV0_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENV0_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENV0_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENV1_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENV1_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENV1_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENV1_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENV1_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENV2_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENV2_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENV2_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENV2_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENV2_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENV3_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENV3_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENV3_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENV3_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENV3_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_00E1|GPUREG_00E1]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_00E4|GPUREG_00E4]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_00E5|GPUREG_00E5]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_00E6|GPUREG_00E6]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_00E8|GPUREG_00E8]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_00E9|GPUREG_00E9]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_00EA|GPUREG_00EA]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_00EB|GPUREG_00EB]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_00EC|GPUREG_00EC]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_00ED|GPUREG_00ED]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_00EE|GPUREG_00EE]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_00EF|GPUREG_00EF]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENV4_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENV4_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENV4_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENV4_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENV4_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENV5_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENV5_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENV5_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENV5_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENV5_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_BLEND_ENABLE|GPUREG_BLEND_ENABLE]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_CONFIG|GPUREG_BLEND_CONFIG]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGICOP_CONFIG|GPUREG_LOGICOP_CONFIG]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_ALPHATEST_CONFIG|GPUREG_ALPHATEST_CONFIG]]
|
|PICA_REG_FRAG_OP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_ACTION|GPUREG_STENCIL_ACTION]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTHTEST_CONFIG|GPUREG_DEPTHTEST_CONFIG]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_0110|GPUREG_0110]]
|?
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_0111|GPUREG_0111]]
|?
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_0118|GPUREG_0118]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_011B|GPUREG_011B]]
|?
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_0120|GPUREG_0120]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_0121|GPUREG_0121]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_0122|GPUREG_0122]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_0123|GPUREG_0123]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_0124|GPUREG_0124]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_0126|GPUREG_0126]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_0130|GPUREG_0130]]
|?
|PICA_REG_FRAG_OP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_0140|GPUREG_0140]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_0141|GPUREG_0141]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_0142|GPUREG_0142]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_0143|GPUREG_0143]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_0144|GPUREG_0144]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_0145|GPUREG_0145]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_0146|GPUREG_0146]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_0147|GPUREG_0147]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_0149|GPUREG_0149]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_014A|GPUREG_014A]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_014B|GPUREG_014B]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_0150|GPUREG_0150]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_0151|GPUREG_0151]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_0152|GPUREG_0152]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_0153|GPUREG_0153]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_0154|GPUREG_0154]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_0155|GPUREG_0155]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_0156|GPUREG_0156]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_0157|GPUREG_0157]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_0159|GPUREG_0159]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_015A|GPUREG_015A]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_015B|GPUREG_015B]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_0160|GPUREG_0160]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_0161|GPUREG_0161]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_0162|GPUREG_0162]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_0163|GPUREG_0163]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_0164|GPUREG_0164]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_0165|GPUREG_0165]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_0166|GPUREG_0166]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_0167|GPUREG_0167]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_0169|GPUREG_0169]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_016A|GPUREG_016A]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_016B|GPUREG_016B]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_0170|GPUREG_0170]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_0171|GPUREG_0171]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_0172|GPUREG_0172]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_0173|GPUREG_0173]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_0174|GPUREG_0174]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_0175|GPUREG_0175]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_0176|GPUREG_0176]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_0177|GPUREG_0177]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_0179|GPUREG_0179]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_017A|GPUREG_017A]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_017B|GPUREG_017B]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_0180|GPUREG_0180]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_0181|GPUREG_0181]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_0182|GPUREG_0182]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_0183|GPUREG_0183]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_0184|GPUREG_0184]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_0185|GPUREG_0185]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_0186|GPUREG_0186]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_0187|GPUREG_0187]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_0189|GPUREG_0189]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_018A|GPUREG_018A]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_018B|GPUREG_018B]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_0190|GPUREG_0190]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_0191|GPUREG_0191]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_0192|GPUREG_0192]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_0193|GPUREG_0193]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_0194|GPUREG_0194]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_0195|GPUREG_0195]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_0196|GPUREG_0196]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_0197|GPUREG_0197]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_0199|GPUREG_0199]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_019A|GPUREG_019A]]
|
|
|-
| 019B
| [[#GPUREG_019B|GPUREG_019B]]
|
|
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_01A0|GPUREG_01A0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_01A1|GPUREG_01A1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_01A2|GPUREG_01A2]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_01A3|GPUREG_01A3]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_01A4|GPUREG_01A4]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_01A5|GPUREG_01A5]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_01A6|GPUREG_01A6]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_01A7|GPUREG_01A7]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_01A9|GPUREG_01A9]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_01AA|GPUREG_01AA]]
|
|
|-
| 01AB
| [[#GPUREG_01AB|GPUREG_01AB]]
|
|
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_01B0|GPUREG_01B0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_01B1|GPUREG_01B1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_01B2|GPUREG_01B2]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_01B3|GPUREG_01B3]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_01B4|GPUREG_01B4]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_01B5|GPUREG_01B5]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_01B6|GPUREG_01B6]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_01B7|GPUREG_01B7]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_01B9|GPUREG_01B9]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_01BA|GPUREG_01BA]]
|
|
|-
| 01BB
| [[#GPUREG_01BB|GPUREG_01BB]]
|
|
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_01C0|GPUREG_01C0]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_01C2|GPUREG_01C2]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_01C3|GPUREG_01C3]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_01C4|GPUREG_01C4]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_01C5|GPUREG_01C5]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_01C6|GPUREG_01C6]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_01C8|GPUREG_01C8]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_01C9|GPUREG_01C9]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_01CA|GPUREG_01CA]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_01CB|GPUREG_01CB]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_01CC|GPUREG_01CC]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_01CD|GPUREG_01CD]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA8
|-
| 01CE
| [[#GPUREG_01CE|GPUREG_01CE]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_01CF|GPUREG_01CF]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_01D0|GPUREG_01D0]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_01D1|GPUREG_01D1]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_01D2|GPUREG_01D2]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_01D9|GPUREG_01D9]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFER0_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFER0_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFER0_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFER1_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFER1_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFER1_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFER2_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFER2_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFER2_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFER3_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFER3_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFER3_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFER4_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFER4_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFER4_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFER5_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFER5_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFER5_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFER6_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFER6_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFER6_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFER7_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFER7_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFER7_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFER8_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFER8_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFER8_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFER9_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFER9_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFER9_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFER10_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFER10_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFER10_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFER11_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFER11_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFER11_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_022D|GPUREG_022D]]
|
|
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_0231|GPUREG_0231]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_0242|GPUREG_0242]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_0244|GPUREG_0244]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_0245|GPUREG_0245]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_024A|GPUREG_024A]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_0251|GPUREG_0251]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_0252|GPUREG_0252]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_0253|GPUREG_0253]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_0254|GPUREG_0254]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_GSH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_GSH_INTUNIFORM_I0|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_GSH_INTUNIFORM_I1|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_GSH_INTUNIFORM_I2|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_GSH_INTUNIFORM_I3|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_GSH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_GSH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_GSH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0292
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0293
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0294
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0295
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0296
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0297
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0298
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_GS_FLOAT_DATA8
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_GSH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_GSH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_VSH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_VSH_INTUNIFORM_I0|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_VSH_INTUNIFORM_I1|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_VSH_INTUNIFORM_I2|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_VSH_INTUNIFORM_I3|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_VSH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_VSH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C2
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C3
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C4
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C5
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C6
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C7
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C8
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
|
|PICA_REG_VS_FLOAT_DATA8
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_VSH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_VSH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

== Texturing registers ==

== Framebuffer registers ==

=== GPUREG_DEPTHBUFFER_FORMAT ===

The format the current depth buffer should be written into. Following values are possible:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 1
| ?? seems to freeze the GPU
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil (stencil is within bit 24-31)
|}

=== GPUREG_COLORBUFFER_FORMAT ===

Describes the format of the current color buffer used for 3D rendering.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?)
|-
| 16-23
| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].

Color components are laid out in reverse byte order, with the most significant bits used first.
|}

== Fragment lighting registers ==

=== GPUREG_01C4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Disable bit for frag light source 0 shadows
|-
| 1
| Disable bit for frag light source 1 shadows
|-
| 2
| Disable bit for frag light source 2 shadows
|-
| 3
| Disable bit for frag light source 3 shadows
|-
| 4
| Disable bit for frag light source 4 shadows
|-
| 5
| Disable bit for frag light source 5 shadows
|-
| 6
| Disable bit for frag light source 6 shadows
|-
| 7
| Disable bit for frag light source 7 shadows
|-
| 8
| Disable bit for frag light source 0 spot
|-
| 9
| Disable bit for frag light source 1 spot
|-
| 10
| Disable bit for frag light source 2 spot
|-
| 11
| Disable bit for frag light source 3 spot
|-
| 12
| Disable bit for frag light source 4 spot
|-
| 13
| Disable bit for frag light source 5 spot
|-
| 14
| Disable bit for frag light source 6 spot
|-
| 15
| Disable bit for frag light source 7 spot
|-
| 24
| Disable bit for frag light source 0 distance attenuation
|-
| 25
| Disable bit for frag light source 1 distance attenuation
|-
| 26
| Disable bit for frag light source 2 distance attenuation
|-
| 27
| Disable bit for frag light source 3 distance attenuation
|-
| 28
| Disable bit for frag light source 4 distance attenuation
|-
| 29
| Disable bit for frag light source 5 distance attenuation
|-
| 30
| Disable bit for frag light source 6 distance attenuation
|-
| 31
| Disable bit for frag light source 7 distance attenuation
|}

== Geometry pipeline registers ==

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
|-
| 8
| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''
|-
| 9-15
| No effect.
|-
| 16-23
| Unknown.
|-
| 24-31
| Unknown. Often set to 0.
|}

This register configures the geometry stage of the GPU pipeline.

=== GPUREG_FIXEDATTRIB_INDEX ===

See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline.
|}

=== GPUREG_FIXEDATTRIB_DATA ===

Accepts a packed 4-tuple of float24 values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].

If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]], but most games seem to write to it before every draw call.
|}

== Geometry shader registers ==

=== GPUREG_GSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the geometry shader unit's boolean registers.

=== GPUREG_GSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i0.w (u8, 0-255)
|}

This register is used to set the geometry shader's i0 integer register.

=== GPUREG_GSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i1.w (u8, 0-255)
|}

This register is used to set the geometry shader's i1 integer register.

=== GPUREG_GSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i2.w (u8, 0-255)
|}

This register is used to set the geometry shader's i2 integer register.

=== GPUREG_GSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for geometry shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for geometry shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for geometry shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for geometry shader's i3.w (u8, 0-255)
|}

This register is used to set the geometry shader's i3 integer register.

=== GPUREG_GSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 8 for geometry shaders.
|}

This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.

=== GPUREG_GSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Geometry shader unit entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 8th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of geometry shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of geometry shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of geometry shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of geometry shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of geometry shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of geometry shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of geometry shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of geometry shader input register which the 16th attribute will be stored in.
|}

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_GSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|}

This register toggles the geometry shader unit's output registers.

=== GPUREG_GSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.

=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_GSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_GSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target geometry shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_GSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader instruction data.
|}

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_GSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target geometry shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.

=== GPUREG_GSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Geometry shader operand descriptor data.
|}

This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

== Vertex shader registers ==

=== GPUREG_VSH_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
|-
| 1
| Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
|-
| 2
| Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
|-
| 3
| Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
|-
| 4
| Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
|-
| 5
| Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
|-
| 6
| Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
|-
| 7
| Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
|-
| 8
| Value of vertex shader unit's b8 boolean register. (0=true, 1=false)
|-
| 9
| Value of vertex shader unit's b9 boolean register. (0=true, 1=false)
|-
| 10
| Value of vertex shader unit's b10 boolean register. (0=true, 1=false)
|-
| 11
| Value of vertex shader unit's b11 boolean register. (0=true, 1=false)
|-
| 12
| Value of vertex shader unit's b12 boolean register. (0=true, 1=false)
|-
| 13
| Value of vertex shader unit's b13 boolean register. (0=true, 1=false)
|-
| 14
| Value of vertex shader unit's b14 boolean register. (0=true, 1=false)
|-
| 15
| Value of vertex shader unit's b15 boolean register. (0=true, 1=false)
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This register is used to set the vertex shader unit's boolean registers.

=== GPUREG_VSH_INTUNIFORM_I0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i0.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i0.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i0.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i0.w (u8, 0-255)
|}

This register is used to set the vertex shader's i0 integer register.

=== GPUREG_VSH_INTUNIFORM_I1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i1.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i1.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i1.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i1.w (u8, 0-255)
|}

This register is used to set the vertex shader's i1 integer register.

=== GPUREG_VSH_INTUNIFORM_I2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i2.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i2.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i2.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i2.w (u8, 0-255)
|}

This register is used to set the vertex shader's i2 integer register.

=== GPUREG_VSH_INTUNIFORM_I3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Value for vertex shader's i3.x (u8, 0-255)
|-
| 8-15
| Value for vertex shader's i3.y (u8, 0-255)
|-
| 16-23
| Value for vertex shader's i3.z (u8, 0-255)
|-
| 24-31
| Value for vertex shader's i3.w (u8, 0-255)
|}

This register is used to set the vertex shader's i3 integer register.

=== GPUREG_VSH_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
|-
| 8-23
| Unknown. These bits typically aren't updated by games.
|-
| 24-31
| Unknown. This is typically set to 0xA for vertex shaders.
|}

This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.

=== GPUREG_VSH_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| Vertex shader entrypoint, in words.
|-
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}

This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 1st attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 2nd attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 3rd attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 4th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 5th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 6th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 7th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 8th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Index of vertex shader input register which the 9th attribute will be stored in.
|-
| 4-7
| Index of vertex shader input register which the 10th attribute will be stored in.
|-
| 8-11
| Index of vertex shader input register which the 11th attribute will be stored in.
|-
| 12-15
| Index of vertex shader input register which the 12th attribute will be stored in.
|-
| 16-19
| Index of vertex shader input register which the 13th attribute will be stored in.
|-
| 20-23
| Index of vertex shader input register which the 14th attribute will be stored in.
|-
| 24-27
| Index of vertex shader input register which the 15th attribute will be stored in.
|-
| 28-31
| Index of vertex shader input register which the 16th attribute will be stored in.
|}

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_VSH_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
|-
| 1
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
|-
| 2
| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
|-
| 3
| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
|-
| 4
| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
|-
| 5
| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
|-
| 6
| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
|-
| 7
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
|-
| 8
| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
|-
| 9
| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
|-
| 10
| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
|-
| 11
| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
|-
| 12
| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
|-
| 13
| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
|-
| 14
| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
|-
| 15
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
|}

This register toggles the vertex shader units' output registers.

=== GPUREG_VSH_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}

This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.

=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
|}

This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

=== GPUREG_VSH_FLOATUNIFORM_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
|}

This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_VSH_CODETRANSFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| Target vertex shader code offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

=== GPUREG_VSH_CODETRANSFER_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader instruction data.
|}

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

=== GPUREG_VSH_OPDESCS_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-6
| Target vertex shader operand descriptor offset for data transfer.
|}

This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.

=== GPUREG_VSH_OPDESCS_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Vertex shader operand descriptor data.
|}

This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

[[Category:GPU]]