ARM11 Interrupts - Revision history

MarcusD: Clarify PDC interrupt use

2021-11-25T18:39:25Z

Clarify PDC interrupt use

← Older revision		Revision as of 21:39, 25 November 2021
Line 88:		Line 88:
	\| 0x2A		\| 0x2A
	\| gsp, TwlBg		\| gsp, TwlBg
	\| PDC0 (VBlank0)		\| PDC0 (Top screen VBlank0, HBlank0)
	\|-		\|-
	\| 0x2B		\| 0x2B
	\| gsp, TwlBg		\| gsp, TwlBg
	\| PDC1 (VBlank1)		\| PDC1 (Bottom screen VBlank1, HBlank1)
	\|-		\|-
	\| 0x2C		\| 0x2C

TuxSH: /* Private Interrupts */

2021-02-04T20:38:53Z

Private Interrupts

← Older revision		Revision as of 23:38, 4 February 2021
Line 18:		Line 18:
	\| 0x1-0x3		\| 0x1-0x3
	\|		\|
	\| MPCore software-interrupt. Used by Boot11 and Kernel11 to kickstart Core1/2/3.		\| MPCore software-interrupt. Used by Boot11 and Kernel11 to kickstart Core1/2/3, and by Kernel11 to sync cores in crt0.
	\|-		\|-
	\| 0x4		\| 0x4
	\| Kernel		\| Kernel
	\| MPCore software-interrupt. Used to manage the performance counter.		\| MPCore software-interrupt. Used to manage the performance counter. Also used by Kernel11 during crt0 to sync up.
	\|-		\|-
	\| 0x5		\| 0x5

TuxSH at 20:52, 4 February 2021

2021-02-04T19:52:04Z

← Older revision		Revision as of 22:52, 4 February 2021
Line 14:		Line 14:
	\| 0		\| 0
	\|		\|
	\| MPCore software-interrupt. ~~Not configured~~.		\| MPCore software-interrupt. Used by Kernel11 to sync cores in crt0.
	\|-		\|-
	\| 0x1-0x3		\| 0x1-0x3

TuxSH: /* Hardware Interrupts */

2021-01-24T21:20:32Z

Hardware Interrupts

← Older revision		Revision as of 00:20, 25 January 2021
Line 244:		Line 244:
	\| 0x63		\| 0x63
	\| gpio, TwlBg		\| gpio, TwlBg
	\| Touch ~~Pen Down~~ (GPIO1_1 falling edge)		\| Touch Screen pressed (GPIO1_1 falling edge)
	\|-		\|-
	\| 0x64		\| 0x64

TuxSH: More GPIOs /* Hardware Interrupts */

2021-01-24T21:14:40Z

More GPIOs Hardware Interrupts

← Older revision		Revision as of 00:14, 25 January 2021
Line 248:		Line 248:
	\| 0x64		\| 0x64
	\| gpio, TwlBg		\| gpio, TwlBg
	\| ~~Headphone jack plugged in/out~~		\| Headphones inserted (GPIO2_0)
	\|-		\|-
	\| 0x66		\| 0x66
	\| gpio, TwlBg		\| gpio, TwlBg
	\| GPIO2_1		\| TWL depop circuit (GPIO2_1)
	\|-		\|-
	\| 0x68		\| 0x68
	\| gpio, TwlBg		\| gpio, TwlBg
	\| C-stick ~~Interrupt~~		\| C-stick interrupt (GPIO3_0)
	\|-		\|-
	\| 0x69		\| 0x69
	\| gpio, TwlBg		\| gpio, TwlBg
	\| IrDA ~~Interrupt~~		\| IrDA interrupt (active-low) (GPIO3_1)
	\|-		\|-
	\| 0x6A		\| 0x6A
	\| gpio, TwlBg		\| gpio, TwlBg
	\| Gyro ~~Interrupt~~		\| Gyro interrupt (GPIO3_2)
	\|-		\|-
	\| 0x6B		\| 0x6B
	\| gpio, TwlBg		\| gpio, TwlBg
	\| GPIO3_3		\| C-stick "stop" (output) (GPIO3_3)
	\|-		\|-
	\| 0x6C		\| 0x6C
	\| gpio, TwlBg		\| gpio, TwlBg
	\| GPIO3_4		\| IrDA TX-RC (output) (GPIO3_4)
	\|-		\|-
	\| 0x6D		\| 0x6D
	\| gpio, TwlBg		\| gpio, TwlBg
	\| GPIO3_5		\| IrDA RXD (GPIO3_5)
	\|-		\|-
	\| 0x6E		\| 0x6E
	\| gpio, TwlBg		\| gpio, TwlBg
	\| GPIO3_6		\| NFC output1 (?) (GPIO3_6)
	\|-		\|-
	\| 0x6F		\| 0x6F
	\| gpio, TwlBg		\| gpio, TwlBg
	\| GPIO3_7		\| NFC output2 (?) (GPIO3_7)
	\|-		\|-
	\| 0x70		\| 0x70
	\| gpio, TwlBg		\| gpio, TwlBg
	\| GPIO3_8		\| Headphones button/half-inserted (active-low) (GPIO3_8)
	\|-		\|-
	\| 0x71		\| 0x71
	\| gpio, TwlBg		\| gpio, TwlBg
	\| MCU (~~HOME/POWER pressed/released or WiFi switch pressed, etc.~~)		\| MCU interrupt (GPIO3_9)
	\|-		\|-
	\| 0x72		\| 0x72
	\| gpio, TwlBg		\| gpio, TwlBg
	\| NFC		\| NFC interrupt (?) (GPIO3_10)
	\|-		\|-
	\| 0x73		\| 0x73
	\| TwlBg		\| TwlBg
	\| GPIO3_11		\| QTM output (?) (GPIO3_11)
	\|-		\|-
	\| 0x74		\| 0x74

TuxSH: /* Hardware Interrupts */

2021-01-24T15:45:28Z

Hardware Interrupts

← Older revision		Revision as of 18:45, 24 January 2021
Line 236:		Line 236:
	\| 0x60		\| 0x60
	\| gpio, TwlBg		\| gpio, TwlBg
	\| Shell opened		\| Shell opened (GPIO1_2 falling edge)
	\|-		\|-
	\| 0x62		\| 0x62
	\| gpio, TwlBg		\| gpio, TwlBg
	\| Shell closed		\| Shell closed (GPIO1_2 rising edge)
	\|-		\|-
	\| 0x63		\| 0x63
	\| gpio, TwlBg		\| gpio, TwlBg
	\| ~~Touchscreen~~ Pen Down		\| Touch Pen Down (GPIO1_1 falling edge)
	\|-		\|-
	\| 0x64		\| 0x64

TuxSH: /* Private Interrupts */

2021-01-21T17:54:20Z

Private Interrupts

← Older revision		Revision as of 20:54, 21 January 2021
Line 16:		Line 16:
	\| MPCore software-interrupt. Not configured.		\| MPCore software-interrupt. Not configured.
	\|-		\|-
	\| 0x1		\| 0x1-0x3
	\|		\|
	\| MPCore software-interrupt. Used by ~~BOOT11~~ to kickstart Core1.		\| MPCore software-interrupt. Used by Boot11 and Kernel11 to kickstart Core1/2/3.
	\|-
	~~\| 0x2-0x3~~
	\|
	~~\| MPCore software-interrupt. Seem to be unused~~.
	\|-		\|-
	\| 0x4		\| 0x4

TuxSH: /* Hardware Interrupts */

2021-01-21T17:48:43Z

Hardware Interrupts

← Older revision		Revision as of 20:48, 21 January 2021
Line 216:		Line 216:
	\| 0x58		\| 0x58
	\| Kernel		\| Kernel
	\| PDN ~~Wake Event~~		\| PDN (wake event or SoC mode changed)
	\|-		\|-
	\| 0x59		\| 0x59
Line 256:		Line 256:
	\| 0x66		\| 0x66
	\| gpio, TwlBg		\| gpio, TwlBg
	\| ~~GPIO_DATA1.bit1 (sfio = ?)~~		\| GPIO2_1
	\|-		\|-
	\| 0x68		\| 0x68
Line 272:		Line 272:
	\| 0x6B		\| 0x6B
	\| gpio, TwlBg		\| gpio, TwlBg
	\| ~~GPIO_DATA3.bit3 (sfio = ?)~~		\| GPIO3_3
	\|-		\|-
	\| 0x6C		\| 0x6C
	\| gpio, TwlBg		\| gpio, TwlBg
	\| ~~GPIO_DATA3.bit4 (sfio = ?)~~		\| GPIO3_4
	\|-		\|-
	\| 0x6D		\| 0x6D
	\| gpio, TwlBg		\| gpio, TwlBg
	\| ~~GPIO_DATA3.bit5 (sfio = ?)~~		\| GPIO3_5
	\|-		\|-
	\| 0x6E		\| 0x6E
	\| gpio, TwlBg		\| gpio, TwlBg
	\| ~~GPIO_DATA3.bit6 (sfio = ?)~~		\| GPIO3_6
	\|-		\|-
	\| 0x6F		\| 0x6F
	\| gpio, TwlBg		\| gpio, TwlBg
	\| ~~GPIO_DATA3.bit7 (sfio = ?)~~		\| GPIO3_7
	\|-		\|-
	\| 0x70		\| 0x70
	\| gpio, TwlBg		\| gpio, TwlBg
	\| ~~GPIO_DATA3.bit8 (sfio = ?)~~		\| GPIO3_8
	\|-		\|-
	\| 0x71		\| 0x71
Line 304:		Line 304:
	\| 0x73		\| 0x73
	\| TwlBg		\| TwlBg
	\| ~~GPIO_DATA3.bit11 (sfio = ?)~~		\| GPIO3_11
	\|-		\|-
	\| 0x74		\| 0x74
Line 330:		Line 330:


	There are 2 tables in the ~~ARM11~~ kernel: the first has 32 * 2(or 32 * 4) 8-byte entries. This table is for the private interrupts that belong to each core. The data for each interrupt can be found by doing table_base + (core_num * 0x100) + (intr_num * 8). The second table is for public hardware interrupts and the data for each interrupt can be retrieved by doing table_base + (intr_num * 8).		There are 2 tables in the Arm11 kernel: the first has 32 * 2(or 32 * 4) 8-byte entries. This table is for the private interrupts that belong to each core. The data for each interrupt can be found by doing table_base + (core_num * 0x100) + (intr_num * 8). The second table is for public hardware interrupts and the data for each interrupt can be retrieved by doing table_base + (intr_num * 8).

	The Arm11 kernel configures interrupts the following way:		The Arm11 kernel configures interrupts the following way (it seems the GPIO IRQ layout doesn't match released 3DS models):

	<nowiki>Interrupts 0x00 to 0x1F: edge-triggered, N-N		<nowiki>Interrupts 0x00 to 0x1F: edge-triggered, N-N

TuxSH: /* Hardware Interrupts */

2021-01-20T19:55:22Z

Hardware Interrupts

← Older revision		Revision as of 22:55, 20 January 2021
Line 225:		Line 225:
	\| mic		\| mic
	\| General microphone interrupt (?)		\| General microphone interrupt (?)
			\|-
			\| 0x5B
			\| -
			\| [[HID_Registers#HID_PAD_CNT\|HID_PAD_CNT]]
	\|-		\|-
	\| 0x5C		\| 0x5C

TuxSH at 01:30, 27 May 2020

2020-05-26T23:30:30Z

← Older revision		Revision as of 03:30, 27 May 2020
Line 330:		Line 330:
	The Arm11 kernel configures interrupts the following way:		The Arm11 kernel configures interrupts the following way:

	<~~code~~>Interrupts 0x00 to 0x1F: edge-triggered, N-N		<nowiki>Interrupts 0x00 to 0x1F: edge-triggered, N-N
	Interrupt 0x20: level-sensitive, 1-N		Interrupt 0x20: level-sensitive, 1-N
	Interrupt 0x21: level-sensitive, 1-N		Interrupt 0x21: level-sensitive, 1-N
Line 409:		Line 409:
	Interrupt 0x7b: level-sensitive, 1-N		Interrupt 0x7b: level-sensitive, 1-N
	Interrupt 0x7c: level-sensitive, 1-N		Interrupt 0x7c: level-sensitive, 1-N
	Interrupt 0x7d: level-sensitive, 1-N</~~code~~>		Interrupt 0x7d: level-sensitive, 1-N</nowiki>

	= InterruptData =		= InterruptData =