DSP Binary - Revision history

Flacs: fix wiki links

2023-11-12T06:29:42Z

fix wiki links

← Older revision		Revision as of 09:29, 12 November 2023
Line 18:		Line 18:
	\| 0x108		\| 0x108
	\| 2		\| 2
	\| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[~~PDN_Registers~~#~~PDN_SHAREDWRAM_32K_DATA~~\|~~PDN_SHAREDWRAM_32K_DATA~~]] and [[~~PDN_Registers~~#~~PDN_SHAREDWRAM_32K_CODE~~\|~~PDN_SHAREDWRAM_32K_CODE~~]], located at physical address 0x10140000 (mapped to 0x1EC40000).		\| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[CONFIG11_Registers#CFG11_SHAREDWRAM_32K_DATA\|CFG11_SHAREDWRAM_32K_DATA]] and [[CONFIG11_Registers#CFG11_SHAREDWRAM_32K_CODE\|CFG11_SHAREDWRAM_32K_CODE]], located at physical address 0x10140000 (mapped to 0x1EC40000).
	\|-		\|-
	\| 0x10C		\| 0x10C

2018-01-16T10:02:03Z

← Older revision		Revision as of 13:02, 16 January 2018
Line 34:		Line 34:
	\| 0x10F		\| 0x10F
	\| 1		\| 1
	\| Flags (bit0=?, bit1=load special segment)		\| Flags:

			bit0: if set, DSP module calls [[DSP:RecvData]] on all three registers and expects them to reply value 1

			bit1: if set, load special segment
	\|-		\|-
	\| 0x110		\| 0x110

2016-08-07T11:25:17Z

Category DSP

← Older revision		Revision as of 15:25, 7 August 2016
Line 1:		Line 1:
	~~[[Category:File formats]]~~

	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! Offset		! Offset
Line 86:		Line 84:

	The normal ending of this files is *.cdc		The normal ending of this files is *.cdc

			[[Category:File formats]]
			[[Category:DSP]]

2016-04-15T12:25:40Z

← Older revision		Revision as of 16:25, 15 April 2016
Line 20:		Line 20:
	\| 0x108		\| 0x108
	\| 2		\| 2
	\| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[~~http://www.3dbrew.org/wiki/~~PDN_Registers#PDN_SHAREDWRAM_32K_DATA\|PDN_SHAREDWRAM_32K_DATA]] and [[~~http://www.3dbrew.org/wiki/~~PDN_Registers#PDN_SHAREDWRAM_32K_CODE\|PDN_SHAREDWRAM_32K_CODE]], located at physical address 0x10140000 (mapped to 0x1EC40000).		\| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[PDN_Registers#PDN_SHAREDWRAM_32K_DATA\|PDN_SHAREDWRAM_32K_DATA]] and [[PDN_Registers#PDN_SHAREDWRAM_32K_CODE\|PDN_SHAREDWRAM_32K_CODE]], located at physical address 0x10140000 (mapped to 0x1EC40000).
	\|-		\|-
	\| 0x10C		\| 0x10C

2016-04-15T12:25:12Z

← Older revision		Revision as of 16:25, 15 April 2016
Line 20:		Line 20:
	\| 0x108		\| 0x108
	\| 2		\| 2
	\| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are (~~u8*)(~~0x1EC40000 ~~+ bit position) (?~~).		\| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are [[http://www.3dbrew.org/wiki/PDN_Registers#PDN_SHAREDWRAM_32K_DATA\|PDN_SHAREDWRAM_32K_DATA]] and [[http://www.3dbrew.org/wiki/PDN_Registers#PDN_SHAREDWRAM_32K_CODE\|PDN_SHAREDWRAM_32K_CODE]], located at physical address 0x10140000 (mapped to 0x1EC40000).
	\|-		\|-
	\| 0x10C		\| 0x10C

2014-11-10T22:11:11Z

Small fixes

← Older revision		Revision as of 01:11, 11 November 2014
Line 24:		Line 24:
	\| 0x10C		\| 0x10C
	\| 1		\| 1
	\| ?		\|?
	\|-		\|-
	\| 0x10D		\| 0x10D
	\| 1		\| 1
	\| Special segment memory type (0=1=0x1FF00000(Program ram)+,2=0x1FF40000(~~Dataram~~)+)		\| Special segment memory type (0=1=0x1FF00000(Program ram)+,2=0x1FF40000(Data ram)+)
	\|-		\|-
	\| 0x10E		\| 0x10E

2014-11-10T22:10:17Z

Clean some things up

← Older revision		Revision as of 01:10, 11 November 2014
Line 16:		Line 16:
	\| 0x104		\| 0x104
	\| 4		\| 4
	\| DSP ~~Binary~~ size		\| DSP binary size
	\|-		\|-
	\| 0x108		\| 0x108
Line 28:		Line 28:
	\| 0x10D		\| 0x10D
	\| 1		\| 1
	\| Special segment ~~Mem~~ type (0=1=0x1FF00000(Program ram)+,2=0x1FF40000(Dataram)+)		\| Special segment memory type (0=1=0x1FF00000(Program ram)+,2=0x1FF40000(Dataram)+)
	\|-		\|-
	\| 0x10E		\| 0x10E
	\| 1		\| 1
	\| Num segments (must be 1..10)		\| Num segments (must be 1-10)
	\|-		\|-
	\| 0x10F		\| 0x10F
	\| 1		\| 1
	\| Flags (bit0=??, bit1=load special segment)		\| Flags (bit0=?, bit1=load special segment)
	\|-		\|-
	\| 0x110		\| 0x110
	\| 4		\| 4
	\| Special segment Start ~~addr~~ in 16-bit words		\| Special segment Start address in 16-bit words
	\|-		\|-
	\| 0x114		\| 0x114
	\| 4		\| 4
	\| Special segment ~~Size~~ in bytes		\| Special segment size in bytes
	\|-		\|-
	\| 0x118		\| 0x118
Line 70:		Line 70:
	\| 4		\| 4
	\| 4		\| 4
	\| Start ~~addr~~ in 16-bit words (must be < 0x20000 for type 0, < 0x10000 for type 1,2)		\| Start address in 16-bit words (must be < 0x20000 for type 0, < 0x10000 for type 1,2)
	\|-		\|-
	\| 8		\| 8
Line 78:		Line 78:
	\| 15		\| 15
	\| 1		\| 1
	\| ~~Mem~~ type (0=1=0x1FF00000(Program ram)+,2=0x1FF40000(Data ram)+)		\| Memory type (0=1=0x1FF00000 (Program ram)+,2=0x1FF40000 (Data ram)+)
	\|-		\|-
	\| 16		\| 16

2014-09-13T12:26:34Z

2014-09-04T16:09:09Z

← Older revision		Revision as of 20:09, 4 September 2014
Line 20:		Line 20:
	\| 0x108		\| 0x108
	\| 2		\| 2
	\| Memory layout (bits 0-7: ~~???~~, 8-15: ~~???~~). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are (u8*)(0x1EC40000 + bit position) (?).		\| Memory layout (bits 0-7: Program ram, 8-15: Data ram). Each bit represents a memory region. The region is always 0x8000 bytes in size (the first region starts at 0x1FF00000; the next is a 0x1FF08000 and so on). The HW registers for DSP memory configuration are (u8*)(0x1EC40000 + bit position) (?).
	\|-		\|-
	\| 0x10C		\| 0x10C
Line 28:		Line 28:
	\| 0x10D		\| 0x10D
	\| 1		\| 1
	\| Special segment Mem type (0=1=0x1FF00000+,2=0x1FF40000+)		\| Special segment Mem type (0=1=0x1FF00000(Program ram)+,2=0x1FF40000(Dataram)+)
	\|-		\|-
	\| 0x10E		\| 0x10E

2014-09-04T16:07:57Z

← Older revision		Revision as of 20:07, 4 September 2014
Line 78:		Line 78:
	\| 15		\| 15
	\| 1		\| 1
	\| Mem type (0=1=0x1FF00000+,2=0x1FF40000+)		\| Mem type (0=1=0x1FF00000(Program ram)+,2=0x1FF40000(Data ram)+)
	\|-		\|-
	\| 16		\| 16