GSP Shared Memory - Revision history

Kynex7510: Use conventional names

2025-05-29T21:10:46Z

Use conventional names

← Older revision		Revision as of 01:10, 30 May 2025
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	Addresses specified in command parameters are virtual addresses. Depending on the command, there might be constraints on the accepted parameters. In general, some commands require parameters to be aligned, and addresses are expected to be on [[Memory_Management#Memory_Mapping\|linear]], [[Memory_layout#0x1F000000_.28New_3DS_only.29\|QTM]] or VRAM memory.		Addresses specified in command parameters are virtual addresses. Depending on the command, there might be constraints on the accepted parameters. In general, some commands require parameters to be aligned, and addresses are expected to be on [[Memory_Management#Memory_Mapping\|linear]], [[Memory_layout#0x1F000000_.28New_3DS_only.29\|QTM]] or VRAM memory.

	=== ~~Trigger DMA Request~~ ===		=== RequestDMA ===

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	Any process must have acquired rendering rights, otherwise the command does nothing.		Any process must have acquired rendering rights, otherwise the command does nothing.

	=== ~~Trigger Command List Processing~~ ===		=== ProcessCommandList ===

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	Any process must have acquired rendering rights, otherwise the command does nothing.		Any process must have acquired rendering rights, otherwise the command does nothing.

	=== ~~Trigger Memory Fill~~ ===		=== MemoryFill ===

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	Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be below its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation.		Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be below its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation.

	=== ~~Trigger Display Transfer~~ ===		=== DisplayTransfer ===

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	No error checking is performed on the parameters. Addresses should be aligned to 8 bytes and should be in linear, QTM or VRAM memory, otherwise PA 0 is used.		No error checking is performed on the parameters. Addresses should be aligned to 8 bytes and should be in linear, QTM or VRAM memory, otherwise PA 0 is used.

	=== ~~Trigger Texture Copy~~ ===		=== TextureCopy ===

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	No error checking is performed on the parameters. Addresses and size should be aligned to 8 bytes, and the addresses should be in linear, QTM or VRAM memory, otherwise PA 0 is used.		No error checking is performed on the parameters. Addresses and size should be aligned to 8 bytes, and the addresses should be in linear, QTM or VRAM memory, otherwise PA 0 is used.

	=== ~~Flush Cache Regions~~ ===		=== FlushCacheRegions ===

	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"

Kynex7510: Add bugs section

2025-05-29T21:08:03Z

Add bugs section

← Older revision		Revision as of 01:08, 30 May 2025
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	\|-		\|-
	\| 2		\| 2
	\| Status (~~bit0~~ = halted, ~~bit7~~ = ~~fatal~~ error)		\| Status (0x1 = halted, 0x80 = error)
	\|-		\|-
	\| 3		\| 3
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	After adding a command, [[GSPGPU:TriggerCmdReqQueue\|TriggerCmdReqQueue]] must be used to start command processing (official code does so when the total commands field is 1).		After adding a command, [[GSPGPU:TriggerCmdReqQueue\|TriggerCmdReqQueue]] must be used to start command processing (official code does so when the total commands field is 1).

	GSP checks for status.bit0 and optionally avoids handling further commands, however the check is done by equality, which means it will always fail if status.bit7 is also set (and thus other commands will be processed). This bug prevents the halting logic from working propertly, but can be worked around by keeping bit0 of word3 set, as that will force halting on each iteration.

	== Commands ==		== Commands ==
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	Any process must have acquired rendering rights, otherwise the error 0xD8202A06 (GSP_NO_RIGHT) is returned.		Any process must have acquired rendering rights, otherwise the error 0xD8202A06 (GSP_NO_RIGHT) is returned.

			== Bugs ==

			* When issuing a DMA request, GSP attempts to acquire an internal semaphore that rules CDMA access; this semaphore is never released on failure paths. While this is generally not an issue, as GSP breaks on DMA failures, it becomes a problem if the DMA request is done with cache flushing: in that case, GSP will error silently, causing a deadlock in DMA code.
			* When handling GX commands apart from RequestDMA and ProcessCommandList, GSP sets the relative busy flags in internal state before executing the commands. This means that, if the relevant interrupts are never triggered (eg. on invalid parameters), the busy flags never get reset, preventing execution of future commands of the same kind.

Kynex7510: lil redesign

2025-05-29T20:45:28Z

lil redesign

← Older revision		Revision as of 00:45, 30 May 2025
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	See [[Configuration Memory]].		See [[Configuration Memory]].

	= Command Queue =		= GX Command Queue =

	~~The~~ command queue is located at sharedMemBase + 0x800 + (clientID * 0x200). It consists of an header followed by at most 15 command entries~~. Each command entry is of size 0x20 and has an header followed by command specific parameters~~.		This command queue is located at sharedMemBase + 0x800 + (clientID * 0x200). It consists of an header followed by at most 15 command entries.

	~~After adding a command, [[GSPGPU~~:~~TriggerCmdReqQueue\|TriggerCmdReqQueue]] must be used to start command processing (official code does so when the total commands field is 1).~~		The queue header has the following structure:

	~~== Command Queue Header ==~~

	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
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	\| Result code for the last command which failed		\| Result code for the last command which failed
	\|}		\|}

			After adding a command, [[GSPGPU:TriggerCmdReqQueue\|TriggerCmdReqQueue]] must be used to start command processing (official code does so when the total commands field is 1).

	GSP checks for status.bit0 and optionally avoids handling further commands, however the check is done by equality, which means it will always fail if status.bit7 is also set (and thus other commands will be processed). This bug prevents the halting logic from working propertly, but can be worked around by keeping bit0 of word3 set, as that will force halting on each iteration.		GSP checks for status.bit0 and optionally avoids handling further commands, however the check is done by equality, which means it will always fail if status.bit7 is also set (and thus other commands will be processed). This bug prevents the halting logic from working propertly, but can be worked around by keeping bit0 of word3 set, as that will force halting on each iteration.

	== ~~Command Header~~ ==		== Commands ==

			A command entry is made of 8 words. The first word is the command header, subsequent words represent command specific parameters.

			The command header has the following structure:

	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
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	\|}		\|}

	~~== Commands ==~~		Addresses specified in command parameters are virtual addresses. Depending on the command, there might be constraints on the accepted parameters. In general, some commands require parameters to be aligned, and addresses are expected to be on [[Memory_Management#Memory_Mapping\|linear]], [[Memory_layout#0x1F000000_.28New_3DS_only.29\|QTM]] or VRAM memory.

	Addresses specified in parameters are virtual addresses. Depending on the command, there might be constraints on the accepted parameters. In general, some commands require parameters to be aligned, and addresses are expected to be on [[Memory_Management#Memory_Mapping\|linear]], [[Memory_layout#0x1F000000_.28New_3DS_only.29\|QTM]] or VRAM memory.

	=== Trigger DMA Request ===		=== Trigger DMA Request ===

Kynex7510: Fix misinformation

2025-05-19T18:55:49Z

Fix misinformation

← Older revision		Revision as of 22:55, 19 May 2025
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	PDC interrupts are sent to all processes; other interrupts are only sent to the process with rendering rights.		PDC interrupts are sent to all processes; other interrupts are only sent to the process with rendering rights.

	~~GSP will only dispatch PSC0 if~~ a [[GSP_Shared_Memory#Trigger_Memory_Fill\|Memory Fill]] command ~~has been issued~~ with both buffers set.		When issuing a [[GSP_Shared_Memory#Trigger_Memory_Fill\|Memory Fill]] command with both buffers set GSP will only dispatch PSC0.

	= Framebuffer Info =		= Framebuffer Info =

Kynex7510: Done edits

2025-05-12T12:54:34Z

Done edits

← Older revision		Revision as of 16:54, 12 May 2025
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	GSP fills the interrupt list, then triggers the event set with [[GSPGPU:RegisterInterruptRelayQueue\|RegisterInterruptRelayQueue]] for the specified process(es).		GSP fills the interrupt list, then triggers the event set with [[GSPGPU:RegisterInterruptRelayQueue\|RegisterInterruptRelayQueue]] for the specified process(es).

	PDC interrupts are sent to all processes; other interrupts are only sent to the process with ~~GPU~~ rights.		PDC interrupts are sent to all processes; other interrupts are only sent to the process with rendering rights.

			GSP will only dispatch PSC0 if a [[GSP_Shared_Memory#Trigger_Memory_Fill\|Memory Fill]] command has been issued with both buffers set.

	= Framebuffer Info =		= Framebuffer Info =
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	== Commands ==		== Commands ==

	Addresses specified in parameters are virtual addresses. ~~Address and size~~ parameters ~~except for command 0~~ and ~~command 5 must~~ be ~~8-byte aligned~~.		Addresses specified in parameters are virtual addresses. Depending on the command, there might be constraints on the accepted parameters. In general, some commands require parameters to be aligned, and addresses are expected to be on [[Memory_Management#Memory_Mapping\|linear]], [[Memory_layout#0x1F000000_.28New_3DS_only.29\|QTM]] or VRAM memory.

	=== Trigger DMA Request ===		=== Trigger DMA Request ===
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	\|}		\|}

	This command issues a [[Corelink_DMA_Engines\|DMA request]] as the ~~calling~~ process. When the destination address is within VRAM, GSP places itself as the destination process, this makes it possible to transfer data in VRAM without needing it listed in the destination process [[NCCH/Extended_Header#ARM11_Kernel_Capabilities\|exheader mappings]]. Otherwise, both source and destination of the DMA request are the ~~calling~~ process.		This command issues a [[Corelink_DMA_Engines\|DMA request]] as the process with [[GSPGPU:AcquireRight\|rendering rights]]. When the destination address is within VRAM, GSP places itself as the destination process: this makes it possible to transfer data in VRAM without needing it listed in the destination process [[NCCH/Extended_Header#ARM11_Kernel_Capabilities\|exheader mappings]]. Otherwise, both source and destination of the DMA request are the process with rendering rights.

	The source buffer must be mapped as readable in the source process, while the destination address must be mapped as writable in the destination process. When flushing is enabled and the source address is above VRAM, ~~[[SVC\|~~svcFlushProcessDataCache]] is used to flush the source buffer.		The source buffer must be mapped as readable in the source process, while the destination address must be mapped as writable in the destination process, otherwise GSP calls [[SVC\|svcBreak]]. When flushing is enabled and the source address is above VRAM, svcFlushProcessDataCache is used to flush the source buffer.

			Any process must have acquired rendering rights, otherwise the command does nothing.

	=== Trigger Command List Processing ===		=== Trigger Command List Processing ===
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	This command sets the [[GPU/External_Registers#Command_List\|Command List registers]], and optionally updates gas additive blend results after command processing has ended.		This command sets the [[GPU/External_Registers#Command_List\|Command List registers]], and optionally updates gas additive blend results after command processing has ended.

	No error checking is performed on the parameters. Address and size should be both aligned to 8 bytes, and the address should be in linear, QTM or VRAM memory, otherwise PA 0 is used. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.		No error checking is performed on the parameters. Address and size should be both aligned to 8 bytes, and the address should be in linear, QTM or VRAM memory, otherwise PA 0 is used. When flushing is enabled, [[SVC\|svcFlushProcessDataCache]] is used to flush the buffer on the process that has acquired rendering rights.

			Any process must have acquired rendering rights, otherwise the command does nothing.

	=== Trigger Memory Fill ===		=== Trigger Memory Fill ===
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	This command sets the [[GPU/External_Registers#Memory_Fill\|Memory Fill registers]].		This command sets the [[GPU/External_Registers#Memory_Fill\|Memory Fill registers]].

	Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be ~~less than~~ its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation.		Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be below its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation.

	=== Trigger Display Transfer ===		=== Trigger Display Transfer ===
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	\|-		\|-
	\| 1		\| 1
	\| ~~Buf0~~ address		\| Buffer 0 address
	\|-		\|-
	\| 2		\| 2
	\| ~~Buf0~~ size		\| Buffer 0 size
	\|-		\|-
	\| 3		\| 3
	\| ~~Buf1~~ address		\| Buffer 1 address
	\|-		\|-
	\| 4		\| 4
	\| ~~Buf1~~ size		\| Buffer 1 size
	\|-		\|-
	\| 5		\| 5
	\| ~~Buf2~~ address		\| Buffer 2 address
	\|-		\|-
	\| 6		\| 6
	\| ~~Buf2~~ size		\| Buffer 2 size
	\|-		\|-
	\| 7		\| 7
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	\|}		\|}

	~~The application~~ buffer ~~addresses specified in~~ the ~~parameters are used with [[SVC\|svcFlushProcessDataCache]]~~. ~~The input buf0~~ size ~~must not be zero~~. ~~When buf1 size is zero~~, ~~svcFlushProcessDataCache() for buf1 and buf2~~ are ~~skipped~~. ~~When buf2 size is zero~~, ~~svcFlushProcessDataCache~~() ~~for buf2~~ is ~~skipped~~.		This command calls svcFlushProcessDataCache for each buffer on the process that has acquired rendering rights.

			If any call fails, its error is returned; If any buffer has size 0, the buffer is skipped. In both cases, subsequent buffers are not processed.

			Any process must have acquired rendering rights, otherwise the error 0xD8202A06 (GSP_NO_RIGHT) is returned.

Kynex7510: TransferEngine

2025-05-12T12:24:26Z

TransferEngine

← Older revision		Revision as of 16:24, 12 May 2025
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	\|}		\|}

	This command sets the ~~GPU~~ [[GPU/External_Registers#Memory_Fill\|Memory Fill registers]].		This command sets the [[GPU/External_Registers#Memory_Fill\|Memory Fill registers]].

	Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be < its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation.		Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be less than its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation.

	=== Trigger Display Transfer ===		=== Trigger Display Transfer ===
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	\|-		\|-
	\| 1		\| 1
	\| ~~Input framebuffer~~ address		\| Source address
	\|-		\|-
	\| 2		\| 2
	\| ~~Output framebuffer~~ address		\| Destination address
	\|-		\|-
	\| 3		\| 3
	\| ~~Input framebuffer [[GPU\|~~dimensions]]		\| Source dimensions
	\|-		\|-
	\| 4		\| 4
	\| Output ~~framebuffer~~ dimensions		\| Output dimensions
	\|-		\|-
	\| 5		\| 5
	~~\| [[GPU~~\|Flags~~]], for applications this is 0x1001000 for the main screen, and 0x1000 for the sub screen.~~		\| Flags
	\|-		\|-
	\| 7-6		\| 7-6
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	\|}		\|}

	This command ~~converts the specified addresses to physical addresses, then writes these physical addresses and parameters to~~ the [[GPU]] registers at 0x1EF00C00. This GPU command copies the already rendered framebuffer data from the input GPU framebuffer address to the specified output LCD framebuffer. The input framebuffer is normally located in VRAM.		This command sets the [[GPU/External_Registers#Transfer_Engine\|Display Transfer registers]].

	~~The GPU color buffer~~ is ~~stored in~~ the ~~same Z-curve (tiled) format as textures~~. ~~By default, SetDisplayTransfer converts the given buffer from the tiled format~~ to a linear ~~format adapted to the LCD framebuffers.~~		No error checking is performed on the parameters. Addresses should be aligned to 8 bytes and should be in linear, QTM or VRAM memory, otherwise PA 0 is used.

	~~Display transfers are performed asynchronously~~, ~~so after requesting a display transfer you should wait for the PPF interrupt to fire before reading the output data.~~

	~~The minimum supported dimension for output~~ is ~~64x64, anything lower will hang the engine~~.

	=== Trigger Texture Copy ===		=== Trigger Texture Copy ===
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	\|-		\|-
	\| 1		\| 1
	\| ~~Input buffer~~ address.		\| Source address
	\|-		\|-
	\| 2		\| 2
	\| ~~Output buffer~~ address.		\| Destination address
	\|-		\|-
	\| 3		\| 3
	\| ~~Total bytes to copy, not including gaps.~~		\| Size
	\|-		\|-
	\| 4		\| 4
	\| ~~Bits 0-15: Size of input line, in bytes. Bits~~ 16~~-31: Gap between input lines, in bytes.~~		\| Line width <nowiki>\|</nowiki> (gap << 16)
	\|-		\|-
	\| 5		\| 5
	\| Same as 4, ~~but~~ for the ~~output.~~		\| Same as above, for the destination
	\|-		\|-
	\| 6		\| 6
	\| Flags, corresponding to the [[GPU/External_Registers#Transfer_Engine\|Transfer Engine flags]]. However, for TextureCopy commands, bit 3 is always set, bit 2 is set if any output dimension is smaller than the input, and other bits are always 0.		\| Flags
	\|-		\|-
	\| 7		\| 7
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	\|}		\|}

	This command ~~is similar to cmd3. It also triggers~~ the [[GPU/External_Registers#~~Transfer_Engine~~\|~~GPU Transfer Engine~~]], ~~but setting~~ the ~~TextureCopy parameters~~.		This command sets the [[GPU/External_Registers#TextureCopy\|Texture Copy registers]]. Note that GSP doesn't enforce bit3 of the flags to be set.

			No error checking is performed on the parameters. Addresses and size should be aligned to 8 bytes, and the addresses should be in linear, QTM or VRAM memory, otherwise PA 0 is used.

	=== Flush Cache Regions ===		=== Flush Cache Regions ===

Kynex7510: PSC + small edits

2025-05-12T12:05:28Z

PSC + small edits

← Older revision		Revision as of 16:05, 12 May 2025
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	\|}		\|}

	This command sets the ~~GPU~~ [[GPU/External_Registers#Command_List\|~~command list~~ registers]], and optionally updates gas additive blend results after command processing has ended.		This command sets the [[GPU/External_Registers#Command_List\|Command List registers]], and optionally updates gas additive blend results after command processing has ended.

	No error checking is performed on the parameters. ~~address~~ and size should be both 8~~-byte aligned~~, and the address should be in linear, QTM or VRAM memory, otherwise PA 0 is ~~returned by the vaddr->paddr conversion code~~. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.		No error checking is performed on the parameters. Address and size should be both aligned to 8 bytes, and the address should be in linear, QTM or VRAM memory, otherwise PA 0 is used. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.

	=== Trigger Memory Fill ===		=== Trigger Memory Fill ===
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	\|-		\|-
	\| 1		\| 1
	\| ~~Buf0~~ start address ~~(0 = don't fill anything)~~		\| Buffer 0 start address
	\|-		\|-
	\| 2		\| 2
	\| ~~Buf0~~ value		\| Buffer 0 value
	\|-		\|-
	\| 3		\| 3
	\| ~~Buf0~~ end address		\| Buffer 0 end address
	\|-		\|-
	\| 4		\| 4
	\| ~~Buf1~~ start address ~~(0 = don't fill anything)~~		\| Buffer 1 start address
	\|-		\|-
	\| 5		\| 5
	\| ~~Buf1~~ value		\| Buffer 1 value
	\|-		\|-
	\| 6		\| 6
	\| ~~Buf1~~ end address		\| Buffer 1 end address
	\|-		\|-
	\| 7		\| 7
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	\|}		\|}

	This command ~~converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to~~ the [[GPU]] ~~registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.~~		This command sets the GPU [[GPU/External_Registers#Memory_Fill\|Memory Fill registers]].
	The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.

	The ~~values of Control0 and Control1 give information about~~ the ~~type of memory fill~~. ~~See [[GPU/External_Registers#Memory Fill\|here]]~~ for ~~more information about memory~~ fill ~~parameters~~.		Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be < its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation.

	=== Trigger Display Transfer ===		=== Trigger Display Transfer ===

Kynex7510: P3D command

2025-05-12T06:30:22Z

P3D command

← Older revision		Revision as of 10:30, 12 May 2025
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	\|}		\|}

	This command ~~converts~~ the ~~specified address to a physical address, then writes the physical address and size to the [[~~GPU~~]] registers at 0x1EF018E0. This buffer contains~~ [[GPU/~~Internal_Registers~~\|~~GPU commands~~]]. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.		This command sets the GPU [[GPU/External_Registers#Command_List\|command list registers]], and optionally updates gas additive blend results after command processing has ended.

			No error checking is performed on the parameters. address and size should be both 8-byte aligned, and the address should be in linear, QTM or VRAM memory, otherwise PA 0 is returned by the vaddr->paddr conversion code. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.

	=== Trigger Memory Fill ===		=== Trigger Memory Fill ===

Kynex7510: Elaborate on GX command 0

2025-05-12T06:03:11Z

Elaborate on GX command 0

← Older revision		Revision as of 10:03, 12 May 2025
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	== Commands ==		== Commands ==

	Addresses specified in parameters are virtual addresses. ~~For applications these are normally located in GSP memory, while for other processes they are located in VRAM.~~		Addresses specified in parameters are virtual addresses. Address and size parameters except for command 0 and command 5 must be 8-byte aligned.

	Address and size parameters except for command 0 and command 5 must be 8-byte aligned.

	=== Trigger DMA Request ===		=== Trigger DMA Request ===
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	\|}		\|}

	This command is ~~normally used~~ to ~~DMA~~ data ~~from~~ the ~~application GSP~~ [[~~Memory_layout~~\|~~heap~~]] ~~to VRAM~~. When flushing is enabled and the source ~~buffer~~ is ~~not located within~~ VRAM, svcFlushProcessDataCache is used to flush the source buffer.		This command issues a [[Corelink_DMA_Engines\|DMA request]] as the calling process. When the destination address is within VRAM, GSP places itself as the destination process, this makes it possible to transfer data in VRAM without needing it listed in the destination process [[NCCH/Extended_Header#ARM11_Kernel_Capabilities\|exheader mappings]]. Otherwise, both source and destination of the DMA request are the calling process.

			The source buffer must be mapped as readable in the source process, while the destination address must be mapped as writable in the destination process. When flushing is enabled and the source address is above VRAM, [[SVC\|svcFlushProcessDataCache]] is used to flush the source buffer.

	=== Trigger Command List Processing ===		=== Trigger Command List Processing ===

Kynex7510: Typo

2025-04-23T13:06:26Z

Typo

← Older revision		Revision as of 17:06, 23 April 2025
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	\|}		\|}

	GSP checks for status.bit0 and optionally avoids handling further commands, however the check is done by equality, which means it will always fail if status.bit7 is also set (and thus other commands will be processed). This bug prevents the halting logic from working propertly, but can worked around by keeping bit0 of word3 set, as that will force halting on each iteration.		GSP checks for status.bit0 and optionally avoids handling further commands, however the check is done by equality, which means it will always fail if status.bit7 is also set (and thus other commands will be processed). This bug prevents the halting logic from working propertly, but can be worked around by keeping bit0 of word3 set, as that will force halting on each iteration.

	== Command Header ==		== Command Header ==