IRQ Registers - Revision history

TuxSH: /* IRQ_IF */

2021-01-29T15:20:20Z

IRQ_IF

← Older revision		Revision as of 18:20, 29 January 2021
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	==IRQ_IF==		==IRQ_IF==
	Bitfield with pending interrupts. See below for the IRQ<->bit mapping.		Bitfield with pending interrupts. See below for the IRQ<->bit mapping.

			Returns the pending interrupt bits on read, clears them on write (writing 0-bits has no effect).

	== Interrupts ==		== Interrupts ==

2017-01-05T23:40:47Z

2015-03-19T20:31:36Z

2015-03-19T20:31:11Z

← Older revision		Revision as of 23:31, 19 March 2015
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	== Registers ==		= Registers =
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! ~~NAME~~		! Old3DS
	! ~~PHYSICAL ADDRESS~~		! Name
	! ~~WIDTH~~		! Address
			! Width
	\|-		\|-
	\| ~~REG_IE~~		\| style="background: green" \| Yes
			\| [[#IRQ_IE\|IRQ_IE]]
	\| 0x10001000		\| 0x10001000
	\| 4		\| 4
	\|-		\|-
	\| ~~REG_IF~~		\| style="background: green" \| Yes
			\| [[#IRQ_IF\|IRQ_IF]]
	\| 0x10001004		\| 0x10001004
	\| 4		\| 4
	\|}		\|}

			==IRQ_IE==
			Bitfield with enabled interrupts. See below for the IRQ<->bit mapping.

			==IRQ_IF==
			Bitfield with pending interrupts. See below for the IRQ<->bit mapping.

	== Interrupts ==		== Interrupts ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! IRQ		! IRQ bit
	! Description		! Description
	\|-		\|-

2014-09-27T19:29:51Z

← Older revision		Revision as of 23:29, 27 September 2014
(No difference)

2012-08-15T22:32:50Z

2012-08-15T22:32:38Z

2012-08-15T22:32:12Z

2012-08-15T22:32:00Z

@@ Line 18: / Line 18: @@
 !  IRQ
 !  Description
 |-
 | 22
-| [[RSA]]
+| [[RSA]
 |}

2012-08-14T03:56:06Z

@@ Line 12: / Line 12: @@
 | 0x10001004
 | 4
 |}