NDMA Registers - Revision history

TuxSH: Add device to device modes

2021-11-10T20:48:54Z

Add device to device modes

@@ Line 1: / Line 1: @@
-DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem. NDMA can access the ARM9 bootrom, including the protected part before it is locked out.
+DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem. NDMA can access the Arm9 bootrom, including the protected part before it is locked out.
 = Registers =
@@ Line 136: / Line 136: @@
 !  Bit
 !  Description
 |-
 |  11-10
@@ Line 168: / Line 171: @@
 |}
-== Startup modes (27-24) ==
+== Startup modes (4-0) ==
 {| class="wikitable" border="1"
 !  Value
@@ Line 192: / Line 195: @@
 |-
 | 6
-| MMC1
+| SDIO1
 |-
 | 7
-| MMC2?
+| SDIO3
 |-
 | 8
@@ Line 207: / Line 210: @@
 |-
 | 11
-| SHA out ([[SHA_Registers#SHA_FIFO|INFIFO]])
+| SHA out ([[SHA_Registers#SHA_FIFO|INFIFO]], source data readback mode)
 |-
 | 12
-| ?
+| NTRCARD
 |-
 | 13
@@ Line 219: / Line 222: @@
 |-
 | 15
-| Boot9 Uses this to copy from the AES out FIFO to the SHA in FIFO
+| Device to device (subclassed by bits 4-0)
 |}

2019-12-17T08:19:05Z

Startup modes (27-24)

← Older revision		Revision as of 11:19, 17 December 2019
Line 219:		Line 219:
	\|-		\|-
	\| 15		\| 15
	\| ~~MMC1 +~~ AES + SHA ~~combined?~~		\| Boot9 Uses this to copy from the AES out FIFO to the SHA in FIFO
	\|}		\|}

2019-05-15T17:46:42Z

Startup modes (27-24)

← Older revision		Revision as of 21:46, 15 May 2019
Line 174:		Line 174:
	\|-		\|-
	\| 0		\| 0
	\| TIMER0?		\| TIMER0
	\|-		\|-
	\| 1		\| 1
	\| TIMER1?		\| TIMER1
	\|-		\|-
	\| 2		\| 2
	\| TIMER2?		\| TIMER2
	\|-		\|-
	\| 3		\| 3
	\| TIMER3?		\| TIMER3
	\|-		\|-
	\| 4		\| 4
Line 192:		Line 192:
	\|-		\|-
	\| 6		\| 6
	\| ?		\| MMC1
	\|-		\|-
	\| 7		\| 7
	\| ~~EMMC~~		\| MMC2?
	\|-		\|-
	\| 8		\| 8
	\| AES ~~WD FREE~~		\| AES in ([[AES_Registers#AES_WRFIFO.2FAES_RDFIFO\|WRFIFO]])
	\|-		\|-
	\| 9		\| 9
	\| AES ~~RD FREE~~		\| AES out ([[AES_Registers#AES_WRFIFO.2FAES_RDFIFO\|RDFIFO]])
	\|-		\|-
	\| 10		\| 10
	\| SHA		\| SHA in ([[SHA_Registers#SHA_FIFO\|INFIFO]])
	\|-		\|-
	\| 11		\| 11
	\| ?		\| SHA out ([[SHA_Registers#SHA_FIFO\|INFIFO]])
	\|-		\|-
	\| 12		\| 12
Line 219:		Line 219:
	\|-		\|-
	\| 15		\| 15
	\| AES + SHA ~~COMBINED~~?		\| MMC1 + AES + SHA combined?
	\|}		\|}

2017-10-20T17:26:16Z

actually add this to wiki

← Older revision		Revision as of 21:26, 20 October 2017
Line 1:		Line 1:
	3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem. NDMA can access the ~~(unprotected)~~ part ~~of the bootrom~~.		3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem. NDMA can access the ARM9 bootrom, including the protected part before it is locked out.

	= Registers =		= Registers =

2017-01-05T23:46:36Z

2017-01-05T23:40:09Z

2017-01-05T23:16:29Z

@@ Line 134: / Line 134: @@
 == NDMA_CNT ==
 {| class="wikitable" border="1"
-!  BIT
+!  Bit
-!  DESCRIPTION
+!  Description
 |-
 |  11-10
@@ Line 167: / Line 167: @@
 |  Enable/busy flag.
 |}
 == Startup modes (27-24) ==
-???
+{| class="wikitable" border="1"
 == Block transfers ==

2015-07-06T18:14:11Z

← Older revision		Revision as of 22:14, 6 July 2015
Line 1:		Line 1:
	3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem.		3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem. NDMA can access the (unprotected) part of the bootrom.

	= Registers =		= Registers =

2015-07-06T18:05:02Z

← Older revision		Revision as of 22:05, 6 July 2015
Line 150:		Line 150:
	\|-		\|-
	\| 19-16		\| 19-16
	\| Block transfer word ~~size~~ = (1<<x) ~~bytes~~.		\| Block transfer word count = (1<<x) words.
	\|-		\|-
	\| 27-24		\| 27-24

2015-07-06T18:00:23Z

← Older revision		Revision as of 22:00, 6 July 2015
Line 62:		Line 62:
	! BIT		! BIT
	! DESCRIPTION		! DESCRIPTION
			\|-
			\| 0
			\| Global enable?
	\|-		\|-
	\| 19-16		\| 19-16
Line 147:		Line 150:
	\|-		\|-
	\| 19-16		\| 19-16
	\| Block transfer word ~~count~~ = (1<<x) ~~words~~.		\| Block transfer word size = (1<<x) bytes.
	\|-		\|-
	\| 27-24		\| 27-24