SPICARD Registers - Revision history

Profi200: /* NSPI_FIFO */

2021-02-14T22:08:11Z

NSPI_FIFO

← Older revision		Revision as of 01:08, 15 February 2021
Line 111:		Line 111:
	\| Data		\| Data
	\|}		\|}

			This FIFO is one way (half-duplex).

	== NSPI_STATUS ==		== NSPI_STATUS ==

2019-06-27T21:42:04Z

Registers

← Older revision		Revision as of 01:42, 28 June 2019
Line 150:		Line 150:
	\|-		\|-
	\| 0		\| 0
	\| Transfer finished? (1 = disabled)		\| Transfer finished (1 = disabled)
	\|-		\|-
	\| 1		\| 1
Line 165:		Line 165:
	\|-		\|-
	\| 0		\| 0
	\| Transfer finished?		\| Transfer finished (also fires on each autopoll try?)
	\|-		\|-
	\| 1		\| 1

2019-05-09T16:51:19Z

Registers: Bit range consistency.

← Older revision		Revision as of 20:51, 9 May 2019
Line 70:		Line 70:
	! DESCRIPTION		! DESCRIPTION
	\|-		\|-
	\| 2-0		\| 0-2
	\| [[Filesystem_services#CardSpiBaudRate\|Baud Rate]]		\| [[Filesystem_services#CardSpiBaudRate\|Baud Rate]]
	\|-		\|-
Line 108:		Line 108:
	! DESCRIPTION		! DESCRIPTION
	\|-		\|-
	\| 31-0		\| 0-31
	\| Data		\| Data
	\|}		\|}

2019-05-09T16:49:01Z

NSPI_BLKLEN

2019-05-09T13:23:44Z

Registers: Added missing registers.

2019-05-07T22:05:00Z

REG_SPICARDCNT

← Older revision		Revision as of 02:05, 8 May 2019
Line 61:		Line 61:
	! DESCRIPTION		! DESCRIPTION
	\|-		\|-
	\| 5-0		\| 2-0
	\| [[Filesystem_services#CardSpiBaudRate\|Baud Rate]]		\| [[Filesystem_services#CardSpiBaudRate\|Baud Rate]]
			\|-
			\| 6-7
			\| Unused device select.
	\|-		\|-
	\| 12		\| 12
Line 73:		Line 76:
	\| Trigger (0 = idle, 1 = busy)		\| Trigger (0 = idle, 1 = busy)
	\|}		\|}

			This register seems to have a bug where the lower 8 bits are shifted up by 16 when reading them back.

	== REG_SPICARDASSERT ==		== REG_SPICARDASSERT ==

2017-04-28T16:35:26Z

← Older revision		Revision as of 20:35, 28 April 2017
Line 74:		Line 74:
	\|}		\|}

	== ~~REG_SPICARDCNT~~ ==		== REG_SPICARDASSERT ==
	When deasserting the card, this registers is set to 0. Presumably contains 1 when the card is asserted.		When deasserting the card, this registers is set to 0. Presumably contains 1 when the card is asserted.

2017-04-28T16:35:05Z

← Older revision		Revision as of 20:35, 28 April 2017
Line 14:		Line 14:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| ?		\| [[#REG_SPICARDASSERT\|REG_SPICARDASSERT]]
	\| 0x1000D804		\| 0x1000D804
	\| 4		\| 4
Line 73:		Line 73:
	\| Trigger (0 = idle, 1 = busy)		\| Trigger (0 = idle, 1 = busy)
	\|}		\|}

			== REG_SPICARDCNT ==
			When deasserting the card, this registers is set to 0. Presumably contains 1 when the card is asserted.

	== REG_SPICARDSIZE ==		== REG_SPICARDSIZE ==

2016-01-21T04:41:37Z

@@ Line 8: / Line 8: @@
 |-
 | style="background: green" | Yes
-| ?
+| [[#REG_SPICARDCNT|REG_SPICARDCNT]]
 | 0x1000D800
 | 4
@@ Line 20: / Line 20: @@
 |-
 | style="background: green" | Yes
-| ?
+| [[#REG_SPICARDSIZE|REG_SPICARDSIZE]]
 | 0x1000D808
 | 4
@@ Line 26: / Line 26: @@
 |-
 | style="background: green" | Yes
-| REG_SPICARDFIFO
+| [[#REG_SPICARDFIFO|REG_SPICARDFIFO]]
 | 0x1000D80C
 | 4
@@ Line 32: / Line 32: @@
 |-
 | style="background: green" | Yes
-| ?
+| [[#REG_SPICARDFIFOSTAT|REG_SPICARDFIFOSTAT]]
 | 0x1000D810
 | 4
@@ Line 54: / Line 54: @@
 | 4
+|
 |}

2015-10-29T01:23:04Z