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Line 4: − A basic implementation of the following specification can be found at [https://github.com/smealum/aemstro]+
nihstro is more advanced than aemstro in a number of areas, hence it makes sense to mention it here.
A compiled shader binary is comprised of two parts : the main instruction sequence and the operand descriptor table. These are both sent to the GPU around the same time but using separate [[GPU Commands]]. Instructions (such as format 1 instruction) may reference operand descriptors. When such is the case, the operand descriptor ID is the offset, in words, of the descriptor within the table.
A compiled shader binary is comprised of two parts : the main instruction sequence and the operand descriptor table. These are both sent to the GPU around the same time but using separate [[GPU Commands]]. Instructions (such as format 1 instruction) may reference operand descriptors. When such is the case, the operand descriptor ID is the offset, in words, of the descriptor within the table.
Both instructions and descriptors are coded in little endian.
Both instructions and descriptors are coded in little endian.
Basic implementations of the following specification can be found at [https://github.com/smealum/aemstro] and [https://github.com/neobrain/nihstro]
Please note that this page is being written as the instruction set is reverse engineered; as such it may very well contain mistakes.
Please note that this page is being written as the instruction set is reverse engineered; as such it may very well contain mistakes.