AES Registers: Difference between revisions
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Vgturtle127 (talk | contribs) m Fixes |
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| Line 88: | Line 88: | ||
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| 4-0 | | 4-0 | ||
| Write | | Write FIFO count (0-16) | ||
|- | |- | ||
| 9-5 | | 9-5 | ||
| Read | | Read FIFO count (0-16) | ||
|- | |- | ||
| 10 | | 10 | ||
| Flush write | | Flush write FIFO (1=Clear write FIFO) | ||
|- | |- | ||
| 11 | | 11 | ||
| Flush read fifo (1=Clear read | | Flush read fifo (1=Clear read FIFO) | ||
|- | |- | ||
| 18-16 | | 18-16 | ||
| Line 103: | Line 103: | ||
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| 19 | | 19 | ||
| ? ( | |? (MAC related) | ||
|- | |- | ||
| 20 | | 20 | ||
| Line 131: | Line 131: | ||
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| 30 | | 30 | ||
| Interrupt enable (1= | | Interrupt enable (1=enable, 0=disable) | ||
|- | |- | ||
| 31 | | 31 | ||
| Start (1= | | Start (1=enable/busy, 0=idle) | ||
|} | |} | ||