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DSP Registers: Difference between revisions

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=Registers=
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  NAME
!  Old3DS
!  PHYSICAL ADDRESS
!  Name
!  WIDTH
!  Address
!  Width
!  Used by
|-
|-
| style="background: green" | Yes
| DSP_PDATA
| DSP_PDATA
| 0x10203000
| 0x10203000
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_PADR
| DSP_PADR
| 0x10203004
| 0x10203004
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_PCFG
| DSP_PCFG
| 0x10203008
| 0x10203008
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_PSTS
| DSP_PSTS
| 0x1020300C
| 0x1020300C
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_PSEM
| DSP_PSEM
| 0x10203010
| 0x10203010
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_PMASK
| DSP_PMASK
| 0x10203014
| 0x10203014
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_PCLEAR
| DSP_PCLEAR
| 0x10203018
| 0x10203018
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_SEM
| DSP_SEM
| 0x1020301C
| 0x1020301C
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_CMD0
| DSP_CMD0
| 0x10203020
| 0x10203020
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_REP0
| DSP_REP0
| 0x10203024
| 0x10203024
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_CMD1
| DSP_CMD1
| 0x10203028
| 0x10203028
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_REP1
| DSP_REP1
| 0x1020302C
| 0x1020302C
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_CMD2
| DSP_CMD2
| 0x10203030
| 0x10203030
| 2
| 2
|
|-
|-
| style="background: green" | Yes
| DSP_REP2
| DSP_REP2
| 0x10203034
| 0x10203034
| 2
| 2
|
|}
|}


=== DSP_PDATA - DSP Transfer Data Read FIFO (R) ===
== DSP_PDATA - DSP Transfer Data Read FIFO (R) ==
0-15  Data (one stage of the 16-stage Read FIFO)
0-15  Data (one stage of the 16-stage Read FIFO)


=== DSP_PDATA - DSP Transfer Data Write FIFO (W)  ===
== DSP_PDATA - DSP Transfer Data Write FIFO (W)  ==
  0-15  Data (one stage of the 16-stage Write FIFO)
  0-15  Data (one stage of the 16-stage Write FIFO)


=== DSP_PADR - DSP Transfer Address (W) ===
== DSP_PADR - DSP Transfer Address (W) ==
  0-15  Lower 16bit of Address in DSP Memory
  0-15  Lower 16bit of Address in DSP Memory
Note: The upper 16bit of Address must be configued in the DMA register (inside
Note: The upper 16bit of Address must be configued in the DMA register (inside of the DSP).
of the DSP).


=== DSP_PCFG - DSP Configuration (R/W)  (16bit) ===
== DSP_PCFG - DSP Configuration (R/W)  (16bit) ==
   0    DSP Reset (0=Release, 1=Reset)  ;should be held "1" for 8 DSP clks
   0    DSP Reset (0=Release, 1=Reset)  ;should be held "1" for 8 DSP clks
   1    Address Auto-Increment (0=Off, 1=On)
   1    Address Auto-Increment (0=Off, 1=On)
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   12-15 DSP Memory Transfer (0=Data Memory, 1=MMIO Register, 5=Program Memory)
   12-15 DSP Memory Transfer (0=Data Memory, 1=MMIO Register, 5=Program Memory)


=== DSP_PSTS - DSP Status (R)          (16bit) ===
== DSP_PSTS - DSP Status (R)          (16bit) ==
   0    Read Transfer Underway Flag  (0=No, 1=Yes/From DSP Memory)
   0    Read Transfer Underway Flag  (0=No, 1=Yes/From DSP Memory)
   1    Write Transfer Underway Flag (0=No, 1=Yes/To DSP Memory)
   1    Write Transfer Underway Flag (0=No, 1=Yes/To DSP Memory)
Line 104: Line 135:
Unknown if/when bit10-15 get reset... maybe after reading the status?
Unknown if/when bit10-15 get reset... maybe after reading the status?


=== DSP_PSEM - ARM11-to-DSP Semaphore        (16bit) ===
== DSP_PSEM - ARM11-to-DSP Semaphore        (16bit) ==
   0-15  DSP-to-ARM11 Semaphore 0..15 Flags (0=Off, 1=On)
   0-15  DSP-to-ARM11 Semaphore 0..15 Flags (0=Off, 1=On)
Reportedly these flags are sent in ARM11-to-DSP direction.
Reportedly these flags are sent in ARM11-to-DSP direction.
Confusingly, the other DSP_Pxxx registers are for opposite direction?
Confusingly, the other DSP_Pxxx registers are for opposite direction?


=== DSP_PMASK - DSP-to-ARM11 Semaphore Mask (16bit) ===
== DSP_PMASK - DSP-to-ARM11 Semaphore Mask (16bit) ==
   0-15  DSP-to-ARM11 Semaphore 0..15 Interrupt Disable (0=Enable, 1=Disable)
   0-15  DSP-to-ARM11 Semaphore 0..15 Interrupt Disable (0=Enable, 1=Disable)


=== DSP_PCLEAR - DSP-to-ARM11 Semaphore Clear (W) (16bit) ===
== DSP_PCLEAR - DSP-to-ARM11 Semaphore Clear (W) (16bit) ==
   0-15  DSP-to-ARM11 Semaphore 0..15 Clear (0=No Change, 1=Clear)
   0-15  DSP-to-ARM11 Semaphore 0..15 Clear (0=No Change, 1=Clear)
Reportedly clears bits in DSP_PSEM. [that's probably nonsense, clearing bits in DSP_SEM would make more sense]
Reportedly clears bits in DSP_PSEM. [that's probably nonsense, clearing bits in DSP_SEM would make more sense]


=== DSP_SEM - DSP-to-ARM11 Semaphore Data (R) (16bit) ===
== DSP_SEM - DSP-to-ARM11 Semaphore Data (R) (16bit) ==
   0-15  DSP-to-ARM11 Semaphore 0..15 Flags (0=Off, 1=On)
   0-15  DSP-to-ARM11 Semaphore 0..15 Flags (0=Off, 1=On)
Reportedly these flags are received in DSP-to-ARM11 direction.
Reportedly these flags are received in DSP-to-ARM11 direction.


=== DSP_CMDX - DSP Command Reg. X (R/W) (ARM11 to DSP) (16bit) ===
== DSP_CMDX - DSP Command Reg. X (R/W) (ARM11 to DSP) (16bit) ==
   0-15  Command/Data to DSP
   0-15  Command/Data to DSP


=== DSP_REPX - DSP Reply Register X (R) (DSP to ARM11) (16bit) ===
== DSP_REPX - DSP Reply Register X (R) (DSP to ARM11) (16bit) ==
   0-15  Reply/Data from DSP
   0-15  Reply/Data from DSP
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