PXI Registers: Difference between revisions

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== Registers ==
= Registers =
{| class="wikitable" border="1"
{| class="wikitable" border="1"
NAME
Old3DS
PHYSICAL ADDRESS
Name
PROCESS VIRTUAL ADDRESS
Address
KERNEL VIRTUAL ADDRESS
Width
WIDTH
Used by
|-
|-
| REG_PXISYNC
| style="background: green" | Yes
| PXI_SYNC9
| 0x10008000
| 4
|
|-
| style="background: green" | Yes
| PXI_CNT9
| 0x10008004
| 4
|
|-
| style="background: green" | Yes
| PXI_RECV_FIFO9
| 0x10008008
| 4
|
|-
| style="background: green" | Yes
| PXI_SYNC11
| 0x10163000
| 0x10163000
| 0x1EC63000
| 0xFFFD2000
| 4
| 4
|
|-
|-
| REG_PXICNT
| style="background: green" | Yes
| PXI_CNT11
| 0x10163004
| 0x10163004
| 0x1EC63004
| 0xFFFD2004
| 4
| 4
|
|-
|-
| REG_PXISEND
| style="background: green" | Yes
| PXI_SEND11
| 0x10163008
| 0x10163008
| 0x1EC63008
| 0xFFFD2008
| 4
| 4
|
|-
|-
| REG_PXIRECV
| style="background: green" | Yes
| PXI_RECV_11
| 0x1016300C
| 0x1016300C
| 0x1EC6300C
| 0xFFFD200C
| 4
| 4
|
|}
|}


The PXI registers are similar to those on DS.


The PXI registers are similar to those on DS.
== PXI_CNT ==
{| class="wikitable" border="1"
!  Bit
!  RW
!  Description
|-
| 0
| R
| Send Fifo Empty Status      (0=Not Empty, 1=Empty)
|-
| 1
| R
| Send Fifo Full Status      (0=Not Full, 1=Full)
|-
| 2
| R/W
| Send Fifo Empty IRQ        (0=Disable, 1=Enable)
|-
| 3
| W
| Send Fifo Clear            (0=Nothing, 1=Flush Send Fifo)
|-
| 8
| R
| Receive Fifo Empty          (0=Not Empty, 1=Empty)
|-
| 9
| R
| Receive Fifo Full          (0=Not Full, 1=Full)
|-
| 10
| R/W
| Receive Fifo Not Empty IRQ  (0=Disable, 1=Enable)
|-
| 14
| R/W
| Error, Read Empty/Send Full (0=No Error, 1=Error/Acknowledge)
|-
| 15
| R/W
| Enable Send/Receive Fifo    (0=Disable, 1=Enable)
|}

Revision as of 02:25, 22 March 2015

Registers

Old3DS Name Address Width Used by
Yes PXI_SYNC9 0x10008000 4
Yes PXI_CNT9 0x10008004 4
Yes PXI_RECV_FIFO9 0x10008008 4
Yes PXI_SYNC11 0x10163000 4
Yes PXI_CNT11 0x10163004 4
Yes PXI_SEND11 0x10163008 4
Yes PXI_RECV_11 0x1016300C 4

The PXI registers are similar to those on DS.

PXI_CNT

Bit RW Description
0 R Send Fifo Empty Status (0=Not Empty, 1=Empty)
1 R Send Fifo Full Status (0=Not Full, 1=Full)
2 R/W Send Fifo Empty IRQ (0=Disable, 1=Enable)
3 W Send Fifo Clear (0=Nothing, 1=Flush Send Fifo)
8 R Receive Fifo Empty (0=Not Empty, 1=Empty)
9 R Receive Fifo Full (0=Not Full, 1=Full)
10 R/W Receive Fifo Not Empty IRQ (0=Disable, 1=Enable)
14 R/W Error, Read Empty/Send Full (0=No Error, 1=Error/Acknowledge)
15 R/W Enable Send/Receive Fifo (0=Disable, 1=Enable)