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GPU/Internal Registers: Difference between revisions

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| 0x0E4
| 0x0E4
|}
|}
This register is used to configure the fragment operation mode and whether to use logic ops or blending.


Fragment operation mode values:
Fragment operation mode values:
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| unsigned, Alpha destination function
| unsigned, Alpha destination function
|}
|}
This register is used to configure the blending function.


Equation values:
Equation values:
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| unsigned, Logic op
| unsigned, Logic op
|}
|}
This register is used to configure the logic op.


Logic op values:
Logic op values:
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| unsigned, Alpha
| unsigned, Alpha
|}
|}
This register is used to configure the blending color.


=== GPUREG_FRAGOP_ALPHA_TEST ===
=== GPUREG_FRAGOP_ALPHA_TEST ===
Line 5,762: Line 5,770:
| unsigned, Reference value
| unsigned, Reference value
|}
|}
This register is used to configure alpha testing.


Function values:
Function values:
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| unsigned, Mask
| unsigned, Mask
|}
|}
This register is used to configure stencil testing.


Function values:
Function values:
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| unsigned, Z-pass operation
| unsigned, Z-pass operation
|}
|}
This register is used to configure stencil result operations.


Operation values:
Operation values:
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| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}
|}
This register is used to depth testing and framebuffer write masking.


Depth function values:
Depth function values:
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| unsigned, Allow read (0 = disable, 0xF = enable)
| unsigned, Allow read (0 = disable, 0xF = enable)
|}
|}
This register configures read access from the color buffer.


=== GPUREG_COLORBUFFER_WRITE ===
=== GPUREG_COLORBUFFER_WRITE ===
Line 6,002: Line 6,020:
| unsigned, Allow write (0 = disable, 0xF = enable)
| unsigned, Allow write (0 = disable, 0xF = enable)
|}
|}
This register configures write access to the color buffer.


=== GPUREG_DEPTHBUFFER_READ ===
=== GPUREG_DEPTHBUFFER_READ ===
Line 6,015: Line 6,035:
| unsigned, Allow depth read (0 = disable, 1 = enable)
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}
|}
This register configures read access from the depth and stencil buffers.


=== GPUREG_DEPTHBUFFER_WRITE ===
=== GPUREG_DEPTHBUFFER_WRITE ===
Line 6,028: Line 6,050:
| unsigned, Allow depth write (0 = disable, 1 = enable)
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}
|}
This register configures write access to the depth and stencil buffers.


=== GPUREG_DEPTHBUFFER_FORMAT ===
=== GPUREG_DEPTHBUFFER_FORMAT ===
Line 6,038: Line 6,062:
| unsigned, Format
| unsigned, Format
|}
|}
This register configures the depth buffer data format.


Format values:
Format values:
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| unsigned, Format
| unsigned, Format
|}
|}
This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.


Pixel size values:
Pixel size values:
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| RGBA4
| RGBA4
|}
|}
Color components are laid out in reverse byte order in memory, with the most significant bits used first.


=== GPUREG_EARLYDEPTH_TEST2 ===
=== GPUREG_EARLYDEPTH_TEST2 ===
Line 6,110: Line 6,137:
| unsigned, Enabled (0 = disabled, 1 = enabled)
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}
|}
This register enables the early depth test.


=== GPUREG_FRAMEBUFFER_BLOCK32 ===
=== GPUREG_FRAMEBUFFER_BLOCK32 ===
Line 6,121: Line 6,150:
|}
|}


To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.
This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.


Render block mode values:
Render block mode values:
Line 6,145: Line 6,174:
| unsigned, Depth buffer physical address >> 3
| unsigned, Depth buffer physical address >> 3
|}
|}
This register configures the depth buffer physical address.


=== GPUREG_COLORBUFFER_LOC ===
=== GPUREG_COLORBUFFER_LOC ===
Line 6,155: Line 6,186:
| unsigned, Color buffer physical address >> 3
| unsigned, Color buffer physical address >> 3
|}
|}
This register configures the color buffer physical address.


=== GPUREG_FRAMEBUFFER_DIM ===
=== GPUREG_FRAMEBUFFER_DIM ===
Line 6,171: Line 6,204:
| 0x1
| 0x1
|}
|}
This register configures the framebuffer dimensions.


=== GPUREG_GAS_LIGHT_XY ===
=== GPUREG_GAS_LIGHT_XY ===
Line 6,187: Line 6,222:
| unsigned, Planar shading density attenuation
| unsigned, Planar shading density attenuation
|}
|}
This register configures gas light planar shading.


=== GPUREG_GAS_LIGHT_Z ===
=== GPUREG_GAS_LIGHT_Z ===
Line 6,203: Line 6,240:
| unsigned, View shading density attenuation
| unsigned, View shading density attenuation
|}
|}
This register configures gas light view shading.


=== GPUREG_GAS_LIGHT_Z_COLOR ===
=== GPUREG_GAS_LIGHT_Z_COLOR ===
Line 6,213: Line 6,252:
| unsigned, View shading effect in line-of-sight direction
| unsigned, View shading effect in line-of-sight direction
|}
|}
This register configures gas light shading in the line-of-sight direction.


=== GPUREG_GAS_LUT_INDEX ===
=== GPUREG_GAS_LUT_INDEX ===
Line 6,223: Line 6,264:
| unsigned, Index
| unsigned, Index
|}
|}
This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.


=== GPUREG_GAS_LUT_DATA ===
=== GPUREG_GAS_LUT_DATA ===
Line 6,234: Line 6,277:
|}
|}


These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAAS_LUT_INDEX.
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.


==== Gas Look-Up Table ====
==== Gas Look-Up Table ====
Line 6,279: Line 6,322:
| fixed0.16.8, Depth direction attenuation proportion
| fixed0.16.8, Depth direction attenuation proportion
|}
|}
This register is used to configure the gas depth direction attenuation proportion.


=== GPUREG_FRAGOP_SHADOW ===
=== GPUREG_FRAGOP_SHADOW ===
Line 6,292: Line 6,337:
| float1.5.10, Penumbra scale with reversed sign
| float1.5.10, Penumbra scale with reversed sign
|}
|}
This register is used to configure shadow properties.


== Fragment lighting registers ==
== Fragment lighting registers ==
Retrieved from "https://www.3dbrew.org/wiki/GPU/Internal_Registers"