Memory layout: Difference between revisions

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=ARM11 ~~Physical memory regions~~ =

= Physical Memory =

== ARM11 ==

{| class="wikitable" border="1"

|-

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==0x17E10000==

===0x17E10000===

The 32bit register at 0x17E10000+0x100 only has bit0 set when, on New3DS, [[PTMSYSM:ConfigureNew3DSCPU]] was used with bit1 set for the input value(the L2 cache flag). All other bits in this register are normally all-zero. Therefore: bit0 set = new cache hardware enabled, clear = new cache hardware disabled(this bit is how the ARM11-kernel checks whether the additional cache hw is enabled).

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* Clears bit0 in 32bit register 0x17E10000+0x100.

=ARM9 ~~Physical memory regions~~ =

=== 0x1F000000 ([[New_3DS]]-only) ===

This area is used by [[QTM Services]](starting at offset 0x200000, size 0x180000). This area is not accessible to the GPU on the old 3DS. The old 3DS and New 3DS GSP module has vaddr->physaddr conversion code for this entire region. On the New 3DS, only the first 0x200000-bytes (half of this memory) are accessible to the GPU.

== ARM9 ==

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==ARM9 MPU ~~regions~~==

==ARM9 MPU Setup==

For the below instruction permissions: RO = memory is executable, while None = not-executable.

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0x01FFFC00 size 0x100-bytes starting with [[9.5.0-22|9.5.0-X]] is the FIRM header used during FIRM-launching.

|}

~~=[[New_3DS]] physical 0x1F000000 memory=~~

This area is used by [[QTM Services]](starting at offset 0x200000, size 0x180000). This area is not accessible to the GPU on the old 3DS. The old 3DS and New 3DS GSP module has vaddr->physaddr conversion code for this entire region. On the New 3DS, only the first 0x200000-bytes (half of this memory) are accessible to the GPU.

=Memory map by firmware=

@@ Line 1: / Line 1: @@
-=ARM11 Physical memory regions =
+= Physical Memory =
+== ARM11 ==
 {| class="wikitable" border="1"
 |-
@@ Line 69: / Line 71: @@
 |}
-==0x17E10000==
+===0x17E10000===
 The 32bit register at 0x17E10000+0x100 only has bit0 set when, on New3DS, [[PTMSYSM:ConfigureNew3DSCPU]] was used with bit1 set for the input value(the L2 cache flag). All other bits in this register are normally all-zero. Therefore: bit0 set = new cache hardware enabled, clear = new cache hardware disabled(this bit is how the ARM11-kernel checks whether the additional cache hw is enabled).
@@ Line 81: / Line 83: @@
 * Clears bit0 in 32bit register 0x17E10000+0x100.
-=ARM9 Physical memory regions =
+=== 0x1F000000 ([[New_3DS]]-only) ===
+This area is used by [[QTM Services]](starting at offset 0x200000, size 0x180000). This area is not accessible to the GPU on the old 3DS. The old 3DS and New 3DS GSP module has vaddr->physaddr conversion code for this entire region. On the New 3DS, only the first 0x200000-bytes (half of this memory) are accessible to the GPU.
+== ARM9 ==
 {| class="wikitable" border="1"
 |-
@@ Line 155: / Line 160: @@
 |}
-==ARM9 MPU regions==
+==ARM9 MPU Setup==
 For the below instruction permissions: RO = memory is executable, while None = not-executable.
@@ Line 550: / Line 555: @@
 x01FFFC00 size 0x100-bytes starting with [[9.5.0-22|9.5.0-X]] is the FIRM header used during FIRM-launching.
 |}
-=[[New_3DS]] physical 0x1F000000 memory=
-This area is used by [[QTM Services]](starting at offset 0x200000, size 0x180000). This area is not accessible to the GPU on the old 3DS. The old 3DS and New 3DS GSP module has vaddr->physaddr conversion code for this entire region. On the New 3DS, only the first 0x200000-bytes (half of this memory) are accessible to the GPU.
 =Memory map by firmware=