AES Registers: Difference between revisions
lol it was already documented on gbatek |
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== Endianness and word order == | == Endianness and word order == | ||
When writing to the AES_CTR, AES_MAC or AES_KEY0/1/2/3 register, the hardware will process the written data according to the current input endianness specified in AES_CNT. | When writing to the AES_CTR, AES_MAC or AES_KEY0/1/2/3 register, the hardware will process the written data according to the current input endianness specified in AES_CNT. This means that the byte ordering within each word is endian swapped accordingly but the word ordering of the register remains little endian. | ||
== CCM mode pitfall == | == CCM mode pitfall == | ||