Video Capture: Difference between revisions

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And the TP to get Clock, Vertical-Sync and Horizontal-Sync.

== Captured Video Control Signals ==

The following picutres show plots of the control signals CLK (TP189), HSYNC (TP190) and VSYNC (TP191). The used sample rate were 50MHz.

The full plot shows about 2.6ms.

[[File:Stp_PCLK_VSYNC_HSYNC_full.jpg|1200px]]

This plot shows 1.28us, mainly featuring the clock

[[File:Stp_PCLK_VSYNC_HSYNC_0..64.jpg|1200px]]

Setup

The signal capturing was done by using an DE10-NANO FPGA development board, Intel signal tap analyzer and 5 wires soldered to the TPs of an EU-O3DS (roughly 25cm long, parallel wired).

VCD and CVS files:

[[Media: Stp_PCLK_VSYNC_HSYNC.7z]]

(to view the VCD file use GTK Wave or similar programs).

== Links ==

@@ Line 19: / Line 19: @@
 | '''13''' || CN2-33 || 172 || R2 || '''21''' || CN1-40 || 174 || G2 || '''17''' || CN1-32 || 176 || B2
 |-
-| '''11''' || CN2-34 || 166 || R3 || '''14''' || CN1-39 || above 180 || G3 || '''23''' || CN1-31 || 170 || B3
+| '''11''' || CN2-34 || 166 || R3 || '''14''' || CN1-39 || 168 (above 180) || G3 || '''23''' || CN1-31 || 170 || B3
 |-
 | '''2'''  || CN2-35 || 183 || R4 || '''22''' || CN1-38 || 185 || G4 || '''5''' || CN1-30 || 187 || B4
@@ Line 25: / Line 25: @@
 | '''3'''  || CN2-36 || 177 || R5 || '''16''' || CN1-37 || 179 || G5 || '''6''' || CN1-29 || 181 || B5
 |-
-| '''1'''  || CN2-37 || 171 || R6 || '''15''' || CN1-36 || below 179 || G6 || '''7''' || CN1-28 || 175 || B6
+| '''1'''  || CN2-37 || 171 || R6 || '''15''' || CN1-36 || 173 (below 179) || G6 || '''7''' || CN1-28 || 175 || B6
 |-
 | '''4'''  || CN2-38 || 165 || R7 || '''9''' || CN1-35 || 167 || G7 || '''8''' || CN1-27 || 169 || B7
@@ Line 44: / Line 44: @@
 And the TP to get Clock, Vertical-Sync and Horizontal-Sync.
+== Captured Video Control Signals ==
+The following picutres show plots of the control signals CLK (TP189), HSYNC (TP190) and VSYNC (TP191). The used sample rate were 50MHz.
+The full plot shows about 2.6ms.
+[[File:Stp_PCLK_VSYNC_HSYNC_full.jpg|1200px]]
+This plot shows 1.28us, mainly featuring the clock
+[[File:Stp_PCLK_VSYNC_HSYNC_0..64.jpg|1200px]]
+Setup
+The signal capturing was done by using an DE10-NANO FPGA development board, Intel signal tap analyzer and 5 wires soldered to the TPs of an EU-O3DS (roughly 25cm long, parallel wired).
+VCD and CVS files:
+[[Media: Stp_PCLK_VSYNC_HSYNC.7z]]
+(to view the VCD file use GTK Wave or similar programs).
 == Links ==