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PDN Services: Difference between revisions

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Register cleanup
 
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|-
| 0x00010000
| 0x00010000
| This loads [[CONFIG11 Registers|CFG11_PTM_0]] and [[CONFIG11 Registers|CFG11_PTM_1]], then writes them to cmdreplyword[2] and cmdreplyword[3].
| GetWakeStatus. This loads [[PDN Registers#PDN_WAKE_ENABLE|PDN_WAKE_ENABLE]] and [[PDN Registers#PDN_WAKE_REASON|PDN_WAKE_REASON]], then writes them to cmdreplyword[2] and cmdreplyword[3].
|-
|-
| 0x00020080
| 0x00020080
| [[CONFIG11 Registers|CFG11_PTM_1]] = cmdword[2] & cmdword[1]. This then writes cmdword[1] to [[CONFIG11 Registers|CFG11_PTM_0]]. [[CONFIG11 Registers|CFG11_PTM_1]] = cmdword[2] & ~cmdword[1].
| ConfigureWakeEvents. [[PDN Registers#PDN_WAKE_REASON|PDN_WAKE_REASON]] = cmdword[2] & cmdword[1]. This then writes cmdword[1] to [[PDN Registers#PDN_WAKE_ENABLE|PDN_WAKE_ENABLE]]. [[PDN Registers#PDN_WAKE_REASON|PDN_WAKE_REASON]] = cmdword[2] & ~cmdword[1].
|-
|-
| 0x00030040
| 0x00030040
| This writes cmdword[1] to [[CONFIG11 Registers|CFG11_PTM_1]].
| Acknowledge. Writes cmdword[1] to [[PDN Registers#PDN_WAKE_REASON|PDN_WAKE_REASON]].
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| 0x000100C0
| 0x000100C0
| (u8 unk0, u8 unk1, u8 unk2) ?controls power to the DSP <just a guess>?
| (bool enable, bool reset, bool deassertResetAfterReset) Enables and/or resets the DSP and/or holds it in reset
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= PDN CODEC Service "pdn:i" =
= PDN I2S Service "pdn:i" =
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
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| 0x00010040
| 0x00010040
| This sets bit0 in [[CONFIG11 Registers#CFG11_CODEC_CNT|CFG11_CODEC_CNT]] to u8 cmd+4.
| This sets bit0 in [[PDN Registers#PDN_I2S1_CNT|PDN_I2S1_CNT]] to u8 cmd+4.
|-
|-
| 0x00020040
| 0x00020040
| This sets bit1 in [[CONFIG11 Registers#CFG11_CODEC_CNT|CFG11_CODEC_CNT]] to u8 cmd+4.
| This sets bit1 in [[PDN Registers#PDN_I2S2_CNT|PDN_I2S2_CNT]] to u8 cmd+4.
|}
|}
Used by [[Codec Services]].


= PDN GSP service "pdn:g" =
= PDN GSP service "pdn:g" =
Line 47: Line 49:
|-
|-
| 0x000100C0
| 0x000100C0
| (u8 value, u32 unk1, u16 unk2) ?controls power to the GPU <just a guess>?
| (bool enableClock, bool resetEngines, bool resetRegisters) Enables and/or resets the GPU, see [[PDN Registers#PDN_GPU_CNT|PDN_GPU_CNT]]
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Line 57: Line 59:
|-
|-
| 0x00010040
| 0x00010040
| This sets bit0 in [[CONFIG11 Registers#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]] to u8 cmd+4.
| This sets bit0 in [[PDN Registers#PDN_CAMERA_CNT|PDN_CAMERA_CNT]] to u8 cmd+4.
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|-
| 0x000200000
| 0x000200000
| This writes [[CONFIG11 Registers#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]] & 1 to u8 cmdreply+8.
| This writes [[PDN Registers#PDN_CAMERA_CNT|PDN_CAMERA_CNT]] & 1 to u8 cmdreply+8.
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