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GPIO Registers: Difference between revisions

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Updated some rtc regs
 
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{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Old3DS
!  Name
!  Name
!  Address
!  Address
!  Width
!  Width
!  GPIO [[GPIO_Services|bitmasks]] associated with this register
|-
|-
| GPIO_DATA0
| style="background: green" | Yes
| [[#GPIOn_DATA|GPIO1_DATA]]
| 0x10147000
| 0x10147000
| 2
| 1
| 0x1, 0x2, 0x4
|-
| style="background: green" | Yes
| [[#GPIOn_DATA|GPIO2_DATA]]
| 0x10147010
| 1
|-
| style="background: green" | Yes
| [[#GPIOn_DIR|GPIO2_DIR]]
| 0x10147011
| 1
|-
| style="background: green" | Yes
| [[#GPIOn_INTCFG|GPIO2_INTCFG]]
| 0x10147012
| 1
|-
|-
| GPIO_DATA1
| style="background: green" | Yes
| [[#0x10147010|0x10147010]]
| [[#GPIOn_INTEN|GPIO2_INTEN]]
| 4
| 0x10147013
| 0x8, 0x10
| 1
|-
|-
| GPIO_DATA2
| style="background: green" | Yes
| [[#GPIOn_DATA2|GPIO2_DATA2]]
| 0x10147014
| 0x10147014
| 2
| 2
| 0x20
|-
|-
| GPIO_DATA3
| style="background: green" | Yes
| [[#GPIOn_DATA|GPIO3_DATA]]
| 0x10147020
| 0x10147020
| 2
| 2
| 0x40, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000
|-
|-
| GPIO_DATA3_INTERRUPT_CLEAR
| style="background: green" | Yes
| [[#GPIOn_DIR|GPIO3_DIR]]
| 0x10147022
| 0x10147022
| 2
| 2
| 0x40, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000
|-
|-
| ??
| style="background: green" | Yes
| [[#GPIOn_INTCFG|GPIO3_INTCFG]]
| 0x10147024
| 0x10147024
| 2
| 2
| 0x40, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000
|-
|-
| ?
| style="background: green" | Yes
| [[#0x10147026|0x10147026]]
| [[#GPIOn_INTEN|GPIO3_INTEN]]
| 0x10147026
| 2
| 2
| ?
|-
|-
| GPIO_DATA4
| style="background: green" | Yes
| [[#GPIOn_DATA2|GPIO3_DATA2]]
| 0x10147028
| 0x10147028
| 2
| 2
| 0x40000
|-
|}
|}


Line 57: Line 73:
!  Description
!  Description
|-
|-
| RTC_CNT (?)
| [[#RTC_CNT_(0x10147100)|RTC_CNT]]
| 0x10147100
| 0x10147100
| 2
| 2
| ???
| Control register
|-
|-
| RTC_REG_STAT1
| RTC_REG_STAT1
Line 71: Line 87:
| 1
| 1
| Rtc status register 2 (command 1). Bitswapped
| Rtc status register 2 (command 1). Bitswapped
|-
| RTC_REG_CLKADJ
| 0x10147112
| 1
| Rtc clock adjustment register (command 6). Bitswapped
|-
|-
| RTC_REG_FREE
| RTC_REG_FREE
Line 77: Line 98:
| The free general purpose rtc register (command 7). Bitswapped
| The free general purpose rtc register (command 7). Bitswapped
|-
|-
| RTC_RAW
| RTC_REG_TIME1
| 0x10147120
| 0x10147120
| 4
| 4
| Byte-wise bit-swapped (bit7 is bit0, etc.) BCD RTC (byte0 = seconds, byte1 = minutes, byte2 = hours, byte3 = day(?))
| Byte-wise bit-swapped (bit7 is bit0, etc.) BCD RTC (byte0 = seconds, byte1 = minutes, byte2 = hours, byte3 = day of week)
|-
|-
| RTC_?
| RTC_REG_TIME2
| 0x10147124
| 0x10147124
| 4
| 4 (3?)
| RTC offset?
| Day, month and year all byte-wise bit-swapped
|-
|-
| RTC_?
| RTC_REG_ALRMTIM1
| 0x10147130
| 0x10147130
| 4
| 4 (3?)
| ???
| Rtc alarm time register 1 (command 4). Byte-wise bit-swapped
|-
|-
| RTC_?
| RTC_REG_ALRMTIM2
| 0x10147134
| 0x10147134
| 4
| 4 (3?)
| ???
| Rtc alarm time register 2 (command 5). Byte-wise bit-swapped
|-
|-
| RTC_?
| RTC_REG_COUNT
| 0x10147140
| 0x10147140
| 4
| 4 (3?)
| Some sort of byte-wise bit-swapped seconds counter
| Rtc dsi counter register (ex command 0). Byte-wise bit-swapped
|-
|-
| RTC_?
| RTC_REG_FOUT1
| 0x10147150
| 0x10147150
| 1
| 1
| ???
| Rtc dsi fout register 1 (ex command 1). Bitswapped
|-
|-
| RTC_?
| RTC_REG_FOUT2
| 0x10147151
| 0x10147151
| 1
| 1
| ???
| Rtc dsi fout register 2 (ex command 2). Bitswapped
|-
|-
| RTC_?
| RTC_REG_ALRMDAT1
| 0x10147160
| 0x10147160
| 4
| 4 (3?)
| ???
| Rtc dsi alarm date register 1 (ex command 4). Byte-wise bit-swapped
|-
|-
| RTC_?
| RTC_REG_ALRMDAT2
| 0x10147164
| 0x10147164
| 4
| 4 (3?)
| ???
| Rtc dsi alarm date register 2 (ex command 5). Byte-wise bit-swapped
|-
|-
|}
|}
Line 126: Line 147:
= Descriptions =
= Descriptions =


== 0x10147010 ==
== GPIO ==
=== GPIO pins ===


{| class="wikitable" border="1"
Only GPIO2 and GPIO3 pins have their interrupts configurable. Active low pins should be configured as "falling edge", and output ports shouldn't have interrupts enabled at all.
!  Bit
!  Description
|-
| 24
| Enable/disable? GPIO interrupt 0x64 (bitmask 0x8)
|-
| 25
| Enable/disable? GPIO interrupt 0x66 (bitmask 0x10)
|}


== 0x10147026 ==
[[GPIO Services]] bitmasks use this table, in that order:


{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bit
!  Bit
!  IRQ ID
!  Description
!  Description
|-
|-
| 0-8
| 0
| ?
| ?
| Debug button (?) (active-low)
|-
|-
| 9
| 1
| Enable/disable interrupt 0x71.
| 0x63 (falling edge)
| Touch Screen (active low, 0 = screen pressed)
|-
|-
| 10-15
| 2
| ?
| 0x60 (falling edge)
|}
0x62 (rising edge)
 
| Shell closed
== GPIO_DATA ==
|-style="border-top: double"
 
| 0
=== GPIO_DATA0 ===
| 0x64
{| class="wikitable" border="1"
| Headphones inserted
!  Bit
!  Description
|-
|-
| 0-2
| 1
| Used for GPIO [[GPIO_Services|bitmask]] 0x7.
| 0x66
| TWL depop circuit (?) (active-low)
|-style="border-top: double"
| DATA2.0
| -
| WiFi mode/freq. select (0 = CTR, 1 = MP (DS WiFi))
|-style="border-top: double"
| 0
| 0x68
| C-stick interrupt
|-
|-
| 1
| 1
| DS EXTKEYIN Pen down (0 = touching, 1 = not touching)
| 0x69
| IrDA interrupt (active-low)
|-
| 2
| 0x6A
| Gyro interrupt
|-
|-
| 3
| 3
| Unused by GPIO-sysmodule and TwlBg.
| 0x6B
| C-stick "stop" (output)
|-
|-
| 4
| 4
| Only used by [[Bootloader|Boot11]].
| 0x6C
| IrDA TX-RC (output)
|-
| 5
| 0x6D
| IrDA RXD (active-low)
|-
| 6
| 0x6E
| NFC output1 (?)
|-
| 7
| 0x6F
| NFC output2 (?)
|-
|-
| 5-15
| 8
| Unused by GPIO-sysmodule and TwlBg.
| 0x70
|}
| Headphones button/half-inserted (active-low)
 
|-
=== GPIO_DATA1 ===
| 9
{| class="wikitable" border="1"
| 0x71
!  Bit
| MCU interrupt
!  Description
|-
| 10
| 0x72
| NFC interrupt (?)
|-
|-
| 0-1
| 11
| Used for GPIO [[GPIO_Services|bitmask]] 0x18.
| 0x73
| QTM output (?)
|-
|-
| 2-31
|-style="border-top: double"
| Unused by GPIO-sysmodule and TwlBg.
| DATA2.0
| -
| WiFi enable
|}
|}


=== GPIO_DATA2 ===
=== GPIOn_DATA ===
Pin values, one bit per pin.
 
=== GPIOn_DIR ===
Pin directions for GPIO2 and GPIO3, one bit per pin.
 
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bit
!  Value
!  Description
!  Description
|-
|-
| 0
| 0
| Used for GPIO [[GPIO_Services|bitmask]] 0x20.
| Input
|-
|-
| 1-15
| 1
| Unused by GPIO-sysmodule and TwlBg.
| Output
|}
|}


=== GPIO_DATA3 ===
=== GPIOn_INTCFG ===
Interrupt configuration for GPIO2 and GPIO3 pins (not the extra ones), one bit per pin.
 
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bit
!  Value
!  Description
!  Description
|-
|-
| 0-11
| 0
| Used for GPIO [[GPIO_Services|bitmask]] 0x3FFC0.
| Falling edge
|-
|-
| 12-31
| 1
| Unused by GPIO-sysmodule and TwlBg.
| Rising edge
|}
|}


=== GPIO_DATA4 ===
=== GPIOn_INTEN ===
Interrupt enable bits for GPIO2 and GPIO3 pins (not the extra ones), one bit per pin.
 
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bit
!  Value
!  Description
!  Description
|-
|-
| 0
| 0
| Used for GPIO [[GPIO_Services|bitmask]] 0x40000.
| Interrupt disabled
|-
|-
| 1-15
| 1
| Unused by GPIO-sysmodule and TwlBg.
| Interrupt enabled
|}
|}


= Default values =
=== GPIOn_DATA2 ===
Extra pins for GPIO2 and GPIO3 (one bit each). These two pins, in total, are not bound to any IRQ and are not configurable.


=== Default values ===
After bootrom initialization, these are the values of the registers:
After bootrom initialization, these are the values of the registers:


Line 251: Line 310:
| 0x10147028
| 0x10147028
| 0x0000
| 0x0000
|}
== Legacy RTC ==
=== RTC_CNT (0x10147100) ===
{| class="wikitable" border="1"
!  Bit
!  Description
|-
| 0
| Latch STAT1
|-
| 1
| Latch STAT2
|-
| 2
| Latch CLKADJ
|-
| 3
| Latch FREE
|-
| 4
| Latch TIME
|-
| 5
| Latch ALRMTIM1
|-
| 6
| Latch ALRMTIM2
|-
| 7
| Latch COUNT
|-
| 8
| Latch FOUT1
|-
| 9
| Latch FOUT2
|-
| 10
| Latch ALRMDAT1
|-
| 11
| Latch ALRMDAT2
|-
| 12
| ARM7 Busy? This may be chipselect
|-
| 13
| ARM7 write command received? (writing 1 clears it seems)
|-
| 14
| ARM7 read command recieved? (writing 1 clears it seems)
|-
| 15
| DS SIO SI pin (rtc irq pin)
|}
|}
Retrieved from "https://www.3dbrew.org/wiki/GPIO_Registers"