517
edits
Changes
→CFG11_SOCINFO
| 1*8
| 1*8
| Boot11, Process9, [[DSP Services]]
| Boot11, Process9, [[DSP Services]]
|-
|-style="border-top: double"
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| [[#CFG11_NULLPAGE_CNT|CFG11_NULLPAGE_CNT]]
| 0x10140100
| 0x10140100
| 2
| 4
|
|
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| Debug related bitfield?
Observed: 0b1100(N3DS)/0b0000(O3DS)
| 0x10140105
| 0x10140105
| 1
| 1
| Kernel11.
|
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 2
| 2
| [[SPI Services]], TwlBg
| [[SPI Services]], TwlBg
|-
|-style="border-top: double"
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| ?
| Enable (0=Disable, 1=Enable)
| Enable (0=Disable, 1=Enable)
|}
|}
== CFG11_NULLPAGE_CNT ==
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0
| Trap all ''data'' accesses to physmem addresses 0x0000 to 0x1000
|-
| 16
| Unknown
|}
The reset value of this register is 0x10000.
== CFG11_FIQ_MASK ==
== CFG11_FIQ_MASK ==
Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1)
Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1)
Reset value: 0xF
== CFG11_CDMA_CNT ==
== CFG11_CDMA_CNT ==
== CFG11_BOOTROM_OVERLAY_VAL ==
== CFG11_BOOTROM_OVERLAY_VAL ==
The 32-bit value to overlay data-reads to bootrom with. See [[PDN Registers#PDN_MPCORE_BOOTCNT|PDN_MPCORE_BOOTCNT]].
The 32-bit value to overlay data-reads to bootrom with. See [[PDN Registers#PDN_LGR_CPU_CNT<0-3>|PDN_LGR_CPU_CNT]]<0-3>.
== CFG11_SOCINFO ==
== CFG11_SOCINFO ==
Read-only register.
Read-only register. Identifies the maximum mode-switching capabilities of the SoC.
* CTR: O3DS
* LGR1: N3DS prototype, 4 cores (orginally 2), up to 535MHz, no L2C (see below)
* LGR2: retail N3DS, 4 cores, up to 804MHz, has L2C
Kernel code suggests that devices that support LGR1 but not LGR2 only had 2 cores. All cores (the number of which can be read from MPCORE SCU registers) are usable in LGR1 mode.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0
| 0
| 1 on both Old3DS and New3DS.
| CTR mode (1 on all 3DSes)
| Boot11
| Boot11
|-
|-
| 1
| 1
| 1 on New3DS.
| LGR1 (1 on all N3DSes, orginally 2 cores, and 2x clockrate)
| Kernel11
| Kernel11
|-
|-
| 2
| 2
| N3DS SoC Mode: if set, use a 3x clock multiplier and 4 cores, otherwise 2x and 2 cores
| LGR2 (1 on all released N3DSes, 4 cores and 3x clockrate)
| Kernel11
| Kernel11
|}
|}