CONFIG11 Registers: Difference between revisions
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| Line 18: | Line 18: | ||
| 1*8 | | 1*8 | ||
| Boot11, Process9, [[DSP Services]] | | Boot11, Process9, [[DSP Services]] | ||
|- | |-style="border-top: double" | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| | | [[#CFG11_NULLPAGE_CNT|CFG11_NULLPAGE_CNT]] | ||
| 0x10140100 | | 0x10140100 | ||
| | | 4 | ||
| | |||
| | |||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| Line 38: | Line 32: | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| ? | | Debug related bitfield? | ||
Observed: 0b1100(N3DS)/0b0000(O3DS) | |||
| 0x10140105 | | 0x10140105 | ||
| 1 | | 1 | ||
| | | | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| Line 72: | Line 61: | ||
| 2 | | 2 | ||
| [[SPI Services]], TwlBg | | [[SPI Services]], TwlBg | ||
|- | |-style="border-top: double" | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| ? | | ? | ||
| Line 155: | Line 144: | ||
| Enable (0=Disable, 1=Enable) | | Enable (0=Disable, 1=Enable) | ||
|} | |} | ||
== CFG11_NULLPAGE_CNT == | |||
{| class="wikitable" border="1" | |||
! Bit | |||
! Description | |||
|- | |||
| 0 | |||
| Trap all ''data'' accesses to physmem addresses 0x0000 to 0x1000 | |||
|- | |||
| 16 | |||
| Unknown | |||
|} | |||
The reset value of this register is 0x10000. | |||
== CFG11_FIQ_MASK == | == CFG11_FIQ_MASK == | ||
Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1) | Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1) | ||
Reset value: 0xF | |||
== CFG11_CDMA_CNT == | == CFG11_CDMA_CNT == | ||
| Line 229: | Line 234: | ||
* CTR: O3DS | * CTR: O3DS | ||
* LGR1: N3DS prototype, 2 | * LGR1: N3DS prototype, 4 cores (orginally 2), up to 535MHz, no L2C (see below) | ||
* LGR2: retail N3DS, 4 cores, has L2C | * LGR2: retail N3DS, 4 cores, up to 804MHz, has L2C | ||
Kernel code suggests that devices that support LGR1 but not LGR2 only had 2 cores. All cores (the number of which can be read from MPCORE SCU registers) are usable in LGR1 mode. | |||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
| Line 242: | Line 249: | ||
|- | |- | ||
| 1 | | 1 | ||
| LGR1 (1 on all N3DSes, 2 cores and 2x clockrate) | | LGR1 (1 on all N3DSes, orginally 2 cores, and 2x clockrate) | ||
| Kernel11 | | Kernel11 | ||
|- | |- | ||