PDN Registers: Difference between revisions
Cleanup →PDN_LGR_SOCMODE |
|||
| Line 433: | Line 433: | ||
N3DS modes (LGR1/LGR2) enable the New 3DS FCRAM extension and are needed to access N3DS-only devices. | N3DS modes (LGR1/LGR2) enable the New 3DS FCRAM extension and are needed to access N3DS-only devices. | ||
* CTR: | * CTR: O3DS | ||
* LGR1: N3DS prototype, 2 | * LGR1: N3DS prototype, 4 cores (originally 2), no L2C | ||
* LGR2: retail N3DS, 4 cores, has L2C | * LGR2: retail N3DS, 4 cores, has L2C | ||
|- | |- | ||
| 15 | | 15 | ||
| | | Interrupt status (read) / clear (write) | ||
|} | |} | ||
'''All currently powered-on cores must be (and remain) in WFI state to trigger the SoC mode switch.''' | |||
Kernel code suggests that devices that support LGR1 but not LGR2 only had 2 cores. All cores (the number of which can be read from MPCORE SCU registers) are usable in LGR1 mode. | |||
On firmlaunch, the kernel sets the mode to O3DS. | On firmlaunch, the kernel sets the mode to O3DS. | ||