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GPU/Shader Instruction Set: Difference between revisions

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== Nomenclature ==
== Nomenclature ==


* opcode names with I appended to them are the same as their non-I version, except they use the inverted instruction format, giving 7 bits to SRC2 (and access to uniforms) and 5 bits to SRC1
* opcode names with I appended to them are the same as their non-I version, except they use the inverted instruction format, giving 7 bits to SRC2 (and access to constant registers) and 5 bits to SRC1


* opcode names with U appended to them are the same as their non-U version, except they are executed conditionally based on the value of a uniform boolean.
* opcode names with U appended to them are the same as their non-U version, except they are executed conditionally based on the value of a constant boolean register.


* opcode names with C appended to them are the same as their non-C version, except they are executed conditionally based on a logical expression specified in the instruction.
* opcode names with C appended to them are the same as their non-C version, except they are executed conditionally based on a logical expression specified in the instruction.
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|}
|}


Format 3 : (used for uniform-based conditional flow control instructions)
Format 3 : (used for constant-based conditional flow control instructions)
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
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|  0x16
|  0x16
|  0x4
|  0x4
|  Uniform ID (BOOL/INT)
|  Constant ID (BOOL/INT)
|-
|-
|  0x1A
|  0x1A
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|  1u
|  1u
|  MOVA
|  MOVA
|  Move to address register; Casts the float uniform given by SRC1 to an integer (truncating the fractional part) and assigns the result to (a0.x, a0.y, _, _), respecting the destination component mask.
|  Move to address register; Casts the float value given by SRC1 to an integer (truncating the fractional part) and assigns the result to (a0.x, a0.y, _, _), respecting the destination component mask.
|-
|-
|  0x13
|  0x13
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== Relative addressing ==
== Relative addressing ==


There are 3 address registers: a0.x, a0.y and aL (loop counter). For format 1 instructions, when IDX != 0, the value of the corresponding address register is added to SRC1's value. For example, if IDX = 2, a0.y = 3 and SRC1 = c8, then instead SRC1+a0.y = c11 will be used for the instruction. It is only possible to use address registers with vector uniform registers, attempting to use them with input attribute or temporary registers results in the address register being ignored (i.e. read as zero).
{| class="wikitable" border="1"
|-
!  IDX raw value
!  Register name
|-
|  0x0
|  None
|-
|  0x1
|  a0.x
|-
|  0x2
|  a0.y
|-
|  0x3
|  aL
|}
 
There are 3 address registers: a0.x, a0.y and aL (loop counter). For format 1 instructions, when IDX != 0, the value of the corresponding address register is added to SRC1's value. For example, if IDX = 2, a0.y = 3 and SRC1 = c8, then instead SRC1+a0.y = c11 will be used for the instruction. It is only possible to use address registers on constant registers, attempting to use them on input attribute or temporary registers results in the address register being ignored (i.e. read as zero).


a0.x and a0.y are set manually through the MOVA instruction by rounding a float value to integer precision. Hence, they may take negative values.
a0.x and a0.y are set manually through the MOVA instruction by rounding a float value to integer precision. Hence, they may take negative values.
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== Registers ==
== Registers ==
Input attribute registers (v0-v7?) store the per-vertex data given by the CPU and hence are read-only.


Output attribute registers (o0-o6) hold the data to be passed to the later GPU stages and are write-only. Each of the output attribute register components is assigned a semantic by setting the corresponding [[GPU_Internal_Registers]].
{| class="wikitable" border="1"
|-
!  Name
!  Format
!  Type
!  Access
!  Written by
!  Description
|-
|  v0-v15
|  vector
|  float
|  Read only
|  Application/Vertex-stream
|  Input registers.
|-
|  o0-o15
|  vector
|  float
|  Write only
|  Vertex shader
|  Output registers.
|-
|  r0-r15
|  vector
|  float
|  Read/Write
|  Vertex shader
|  Temporary registers.
|-
|  c0-c95
|  vector
|  float
|  Read only
|  Application
|  Floating-point Constant registers.
|-
|  i0-i3
|  vector
|  integer
|  Read only
|  Application
|  Integer Constant registers. (special purpose)
|-
|  b0-b15
|  scalar
|  boolean
|  Read only
|  Application
|  Boolean Constant registers. (special purpose)
|-
|  a0.x & a0.y
|  scalar
|  integer
|  Use/Write
|  Vertex shader
|  Address registers.
|-
|  aL
|  scalar
|  integer
|  Use
|  Application
|  Loop count register.
|}
 
Input attribute registers store the per-vertex data given by the CPU and hence are read-only.


Uniform registers hold user-specified data which is constant throughout all processed vertices. There are 96 float[4] uniform registers (c0-c95), eight boolean registers (b0-b7), and four int[4] registers (i0-i3).
Output attribute registers hold the data to be passed to the later GPU stages and are write-only. Each of the output attribute register components is assigned a semantic by setting the corresponding [[GPU_Internal_Registers]]. Output registers o7-o15 are only available in vertex shaders.
It appears that writing twice to a component of an output register that was written to before can cause problems (e.g. GPU hangs).


Temporary registers (r0-r15) can be used for intermediate calculations and can both be read and written.
Temporary registers can be used for intermediate calculations and can be both read and written.


Many shader instructions which take float arguments have only 5 bits available for the second argument. They may hence only refer to input attributes or temporary registers. In particular, it's not possible to pass two float[4] uniforms to these instructions.
Constant registers hold data uploaded by the application which remain constant throughout all processed vertices. There are 96 float[4] constant registers (c0-c95), eight boolean constant registers (b0-b7), and four int[4] constant registers (i0-i3).
Many shader instructions which take float arguments can only provide the full 7 bits for one SRC operand. All other source operands can only be used to refer to input attributes or temporary registers and cannot be passed Floating-point Constant registers.


It appears that writing twice to the same output register can cause problems (e.g. GPU hangs).
Address registers and the Loop count register can be used to to provide relative addressing for the designated SRC operand. For more information, see the section on [[#Relative_addressing|relative addressing]].


DST mapping :
DST mapping :
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|  0x20-0x7F
|  0x20-0x7F
|  c0-c95
|  c0-c95
|  Vector uniform registers.
|  Constant registers.
|}
|}


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