GSP Shared Memory: Difference between revisions
PSC + small edits |
TransferEngine |
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This command sets the | This command sets the [[GPU/External_Registers#Memory_Fill|Memory Fill registers]]. | ||
Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be | Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be less than its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation. | ||
=== Trigger Display Transfer === | === Trigger Display Transfer === | ||
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|- | |- | ||
| 1 | | 1 | ||
| | | Source address | ||
|- | |- | ||
| 2 | | 2 | ||
| | | Destination address | ||
|- | |- | ||
| 3 | | 3 | ||
| | | Source dimensions | ||
|- | |- | ||
| 4 | | 4 | ||
| Output | | Output dimensions | ||
|- | |- | ||
| 5 | | 5 | ||
| Flags | |||
|- | |- | ||
| 7-6 | | 7-6 | ||
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This command | This command sets the [[GPU/External_Registers#Transfer_Engine|Display Transfer registers]]. | ||
No error checking is performed on the parameters. Addresses should be aligned to 8 bytes and should be in linear, QTM or VRAM memory, otherwise PA 0 is used. | |||
=== Trigger Texture Copy === | === Trigger Texture Copy === | ||
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|- | |- | ||
| 1 | | 1 | ||
| | | Source address | ||
|- | |- | ||
| 2 | | 2 | ||
| | | Destination address | ||
|- | |- | ||
| 3 | | 3 | ||
| | | Size | ||
|- | |- | ||
| 4 | | 4 | ||
| | | Line width <nowiki>|</nowiki> (gap << 16) | ||
|- | |- | ||
| 5 | | 5 | ||
| Same as | | Same as above, for the destination | ||
|- | |- | ||
| 6 | | 6 | ||
| Flags | | Flags | ||
|- | |- | ||
| 7 | | 7 | ||
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|} | |} | ||
This command | This command sets the [[GPU/External_Registers#TextureCopy|Texture Copy registers]]. Note that GSP doesn't enforce bit3 of the flags to be set. | ||
No error checking is performed on the parameters. Addresses and size should be aligned to 8 bytes, and the addresses should be in linear, QTM or VRAM memory, otherwise PA 0 is used. | |||
=== Flush Cache Regions === | === Flush Cache Regions === |