GPU/External Registers: Difference between revisions

| DisplayTransfer output width (bits 0-15) and height (bits 16-31).

| DisplayTransfer input width and height.

| Transfer flags. (See below)

| GSP module writes value 0 here prior to writing to 0x1EF00C18, for cmd3.

|  Setting bit0 starts the transfer. Upon completion, bit0 is unset and bit8 is set.

| TextureCopy total amount of data to copy, in bytes.

| TextureCopy input line width (bits 0-15) and gap (bits 16-31), in 16 byte units.

| TextureCopy output line width and gap.

These registers are used by [[GSP_Shared_Memory|GX command]] 3 and 4. For cmd4, *0x1EF00C18 |= 1 is used instead of just writing value 1. The DisplayTransfer registers are only used if bit 3 of the flags is unset and ignored otherwise. The TextureCopy registers are likewise only used if bit 3 is set, and ignored otherwise.

| When set, the framebuffer data is flipped vertically.

| When set, the input framebuffer is treated as linear and converted to tiled in the output, converts tiled->linear when unset.

| This bit is required when the output width is less than the input width for the hardware to properly crop the lines, otherwise the output will be mis-aligned.

| Uses a TextureCopy mode transfer. See below for details.

| Don't perform tiled-linear conversion. Incompatible with bit 1, so only tiled-tiled transfers can be done, not linear-linear.

| Input framebuffer color format, value0 and value1 are the same as the [[GPU Registers#Framebuffer_color_formats|LCD Source Framebuffer Formats]] (usually zero)

| Output framebuffer color format

| Use 32x32 block tiling mode, instead of the usual 8x8 one. Output dimensions must be multiples of 32, even if cropping with bit 2 set above.

| Scale down the input image using a box filter. 0 = No downscale, 1 = 2x1 downscale. 2 = 2x2 downscale, 3 = invalid