GPU/Pitfalls: Difference between revisions

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=== Vertex attribute alignment ===

Vertex components which are defined through [[GPU/Internal_Registers#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFERi_CONFIG1]] will be aligned.

Vertex components which are defined through [[GPU/Internal_Registers#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFERi_CONFIG1]] will be accessed aligned by the GPU.

* Vertex attributes will be aligned to their component element size.

* Padding attributes (Component type > 11) will always aligned to 4 byte offets into the buffer.

* The stride which is passed to the GPU should be passed unaligned.

=== Vertex stride in GPUREG_ATTRIBBUFFERi_CONFIG2 ===

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=== Output mapping in GPUREG_SH_OUTMAP_MASK ===

The output ~~mapping~~ in [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_MASK|GPUREG_SH_OUTMAP_MASK]] ~~configures~~ how the registers starting at [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_Oi]] ~~will~~ map ~~the~~ outputs in the shader.

The output masking in [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_MASK|GPUREG_SH_OUTMAP_MASK]] influences how the registers starting at [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_Oi]] map to outputs in the shader.

If an output is disabled in [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_MASK|GPUREG_SH_OUTMAP_MASK]] it means that no slot in the [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_Oi]] registers is consumed.

[[GPU/Internal_Registers#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]] configures the number of used consecutive slots in the outmap.

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|(unused)

|}

=== TEXUNIT1 Corruption and Instability ===

If an L4-formatted texture (or likely any 4-bit texture format) located within VRAM is bound to TEXUNIT1, the PICA can become unstable, usually freezing after a seemingly random amount of time. If that texture is 8x16 or larger, the GPU will also display corrupt visuals until the console is rebooted; this will even persist in other software. Unbinding the texture makes the console stable again, but doesn't fix the visuals, though the severity of the corruption is slightly reduced because the exact results also depend on the texture data. Notably, this does not seem to occur with other TEXUNITs or with textures located in FCRAM. This could use more investigation.

Writer's Note: I struggled for days to reproduce this. I happened across it in a real application, and swapping between L4 and L8 affected the issue with 100% consistency. I then went to make this write-up months later and made a test program to reproduce the bug, which worked as expected. Like a doofus I rewrote the program a bit to test a bit more thoroughly, somehow caused the bug to stop occurring, and haven't been able to reproduce it since. Needs further investigation.

== Shaders ==

=== ~~Write output~~ components exactly once ===

=== Configued Output components must be written exactly once ===

Each configured output component has to be written exactly once or the PICA freezes.

@@ Line 7: / Line 7: @@
 === Vertex attribute alignment ===
-Vertex components which are defined through [[GPU/Internal_Registers#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFERi_CONFIG1]] will be aligned.
+Vertex components which are defined through [[GPU/Internal_Registers#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFERi_CONFIG1]] will be accessed aligned by the GPU.
 * Vertex attributes will be aligned to their component element size.
 * Padding attributes (Component type > 11) will always aligned to 4 byte offets into the buffer.
+* The stride which is passed to the GPU should be passed unaligned.
 === Vertex stride in GPUREG_ATTRIBBUFFERi_CONFIG2 ===
@@ Line 19: / Line 20: @@
 === Output mapping in GPUREG_SH_OUTMAP_MASK ===
-The output mapping in [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_MASK|GPUREG_SH_OUTMAP_MASK]] configures how the registers starting at [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_Oi]] will map the outputs in the shader.
+The output masking in [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_MASK|GPUREG_SH_OUTMAP_MASK]] influences how the registers starting at [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_Oi]] map to outputs in the shader.
 If an output is disabled in [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_MASK|GPUREG_SH_OUTMAP_MASK]] it means that no slot in the [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_Oi]] registers is consumed.
 [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]] configures the number of used consecutive slots in the outmap.
@@ Line 50: / Line 52: @@
 |(unused)
 |}
+=== TEXUNIT1 Corruption and Instability ===
+If an L4-formatted texture (or likely any 4-bit texture format) located within VRAM is bound to TEXUNIT1, the PICA can become unstable, usually freezing after a seemingly random amount of time. If that texture is 8x16 or larger, the GPU will also display corrupt visuals until the console is rebooted; this will even persist in other software. Unbinding the texture makes the console stable again, but doesn't fix the visuals, though the severity of the corruption is slightly reduced because the exact results also depend on the texture data. Notably, this does not seem to occur with other TEXUNITs or with textures located in FCRAM. This could use more investigation.
+Writer's Note: I struggled for days to reproduce this. I happened across it in a real application, and swapping between L4 and L8 affected the issue with 100% consistency. I then went to make this write-up months later and made a test program to reproduce the bug, which worked as expected. Like a doofus I rewrote the program a bit to test a bit more thoroughly, somehow caused the bug to stop occurring, and haven't been able to reproduce it since. Needs further investigation.
 == Shaders ==
-=== Write output components exactly once ===
+=== Configued Output components must be written exactly once ===
 Each configured output component has to be written exactly once or the PICA freezes.