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Output (WO) registers are also located within the 0x0-0x10 range. What data they are contain is specified by the CPU.
Output (WO) registers are also located within the 0x0-0x10 range. What data they are contain is specified by the CPU.
Registers within the 0x20-0x40 ranges seem to be RW. They contain uniforms, such as matrix data.
Registers within the 0x20-0x40 ranges seem to be RW. They contain uniforms, such as matrix data.
It appears that SRC1 and SRC2 operands don't map to registers in the same way. SRC1 is mapped to RO input registers (attributes and uniforms), while SRC2 is mapped to RW register and some RO input registers (attributes). DST is mapped to WO output registers and RW registers. As such, a register written to by an instruction cannot be referenced by SRC1, but it can be referenced by SRC2.
It appears that writing twice to the same output register can cause problems, such as the GPU hanging.
It appears that writing twice to the same output register can cause problems, such as the GPU hanging.