IRQ Registers: Difference between revisions
No edit summary |
|||
(2 intermediate revisions by one other user not shown) | |||
Line 5: | Line 5: | ||
! Address | ! Address | ||
! Width | ! Width | ||
! Used by | |||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
Line 10: | Line 11: | ||
| 0x10001000 | | 0x10001000 | ||
| 4 | | 4 | ||
| Boot9, Kernel9 | |||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
Line 15: | Line 17: | ||
| 0x10001004 | | 0x10001004 | ||
| 4 | | 4 | ||
| Boot9, Kernel9 | |||
|} | |} | ||
Line 22: | Line 25: | ||
==IRQ_IF== | ==IRQ_IF== | ||
Bitfield with pending interrupts. See below for the IRQ<->bit mapping. | Bitfield with pending interrupts. See below for the IRQ<->bit mapping. | ||
Returns the pending interrupt bits on read, clears them on write (writing 0-bits has no effect). | |||
== Interrupts == | == Interrupts == |