PXI Registers: Difference between revisions

← Older edit

@@ Line 1: / Line 1: @@
-= Protocol =
-The communication protocol for normal PXI commands is documented below. The size of cmd_buf is calculated from the cmd_hdr. Total size for command header + buffer must be at most 0x40 bytes, otherwise Process9 will panic.
-==Request==
- A11->A9 (u32) pxi_id
- A11->A9 (u32) cmd_hdr
- A11->A9 (u32[]) cmd_buf
-==Response==
- A9->A11 (u32) pxi_id
- A9->A11 (u32) cmd_hdr
- A9->A11 (u32[]) cmd_buf
 = Registers =
 {| class="wikitable" border="1"
@@ Line 24: / Line 11: @@
 | 0x10008000
 | 4
-|
+| Boot9, Process9
 |-
 | style="background: green" | Yes
 | [[#PXI_CNT|PXI_CNT]]9
 | 0x10008004
+| 2
+| Boot9, Process9
+|-
+| style="background: green" | Yes
+| PXI_SEND9
+| 0x10008008
 | 4
 |
 |-
 | style="background: green" | Yes
-| PXI_RECV_FIFO9
+| PXI_RECV9
-| 0x10008008
+| 0x1000800C
 | 4
 |
@@ Line 42: / Line 35: @@
 | 0x10163000
 | 4
-|
+| Boot11
 |-
 | style="background: green" | Yes
 | [[#PXI_CNT|PXI_CNT]]11
 | 0x10163004
-| 4
+| 2
-|
+| Boot11
 |-
 | style="background: green" | Yes
@@ Line 57: / Line 50: @@
 |-
 | style="background: green" | Yes
-| PXI_RECV_11
+| PXI_RECV11
 | 0x1016300C
 | 4
@@ Line 71: / Line 64: @@
 !  Description
 |-
-| 0-3
+| 0-7
 | R
-| Data input from PXI_SYNC Bit8-11 of remote CPU (00h..0Fh)
+| Data received from remote bits 8-15 (unrelated to SEND/RECV FIFOs)
 |-
-| 8-11
+| 8-15
 | R/W
-| Data output to PXI_SYNC Bit0-3 of remote CPU   (00h..0Fh)
+| Data sent to remote bits 0-7
 |-
-| 13
+| 23
-| W
+| ?
-| Send IRQ to remote CPU      (0=None, 1=Send IRQ)
+| ?
 |-
-| 14
+| 29
-| R/W
+| W?
-| Enable IRQ from remote CPU  (0=Disable, 1=Enable)
+| Trigger PXI_SYNC11 IRQ (if enabled)
+|-
+| 30
+| W?
+| Trigger PXI_SYNC9 IRQ (if enabled)
+|-
+| 31
+| RW
+| PXI_SYNC IRQ enable (for local processor)
 |}
+This can also be accessed as 4 u8 registers.
 == PXI_CNT ==