NDMA Registers: Difference between revisions
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3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem. NDMA can access the | 3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem. NDMA can access the Arm9 bootrom, including the protected part before it is locked out. | ||
= Registers = | = Registers = | ||
| Line 13: | Line 13: | ||
| 0x10002000 | | 0x10002000 | ||
| 4 | | 4 | ||
| | | Boot9, Kernel9 | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| Line 19: | Line 19: | ||
| 0x10002004 + (n*0x1c) | | 0x10002004 + (n*0x1c) | ||
| 4 | | 4 | ||
| | | Boot9, Kernel9 | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| Line 25: | Line 25: | ||
| 0x10002008 + (n*0x1c) | | 0x10002008 + (n*0x1c) | ||
| 4 | | 4 | ||
| | | Boot9, Kernel9 | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| Line 31: | Line 31: | ||
| 0x1000200c + (n*0x1c) | | 0x1000200c + (n*0x1c) | ||
| 4 | | 4 | ||
| | | Boot9, Kernel9 | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| Line 37: | Line 37: | ||
| 0x10002010 + (n*0x1c) | | 0x10002010 + (n*0x1c) | ||
| 4 | | 4 | ||
| | | Boot9, Kernel9 | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| Line 43: | Line 43: | ||
| 0x10002014 + (n*0x1c) | | 0x10002014 + (n*0x1c) | ||
| 4 | | 4 | ||
| | | Boot9, Kernel9 | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| Line 49: | Line 49: | ||
| 0x10002018 + (n*0x1c) | | 0x10002018 + (n*0x1c) | ||
| 4 | | 4 | ||
| | | Boot9, Kernel9 | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| Line 55: | Line 55: | ||
| 0x1000201C + (n*0x1c) | | 0x1000201C + (n*0x1c) | ||
| 4 | | 4 | ||
| | | Boot9, Kernel9 | ||
|} | |} | ||
== NDMA_GLOBAL_CNT == | == NDMA_GLOBAL_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! | ! Bit | ||
! | ! Description | ||
|- | |- | ||
| 0 | | 0 | ||
| Global enable? | | Global enable? | ||
|- | |- | ||
| 19-16 | | 19-16 | ||
| Line 75: | Line 75: | ||
== NDMA_SRC_ADDR == | == NDMA_SRC_ADDR == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! | ! Bit | ||
! | ! Description | ||
|- | |- | ||
| 31-0 | | 31-0 | ||
| Line 95: | Line 95: | ||
== NDMA_TRANSFER_CNT == | == NDMA_TRANSFER_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! | ! Bit | ||
! | ! Description | ||
|- | |- | ||
| 27-0 | | 27-0 | ||
| Line 104: | Line 104: | ||
== NDMA_WRITE_CNT == | == NDMA_WRITE_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! | ! Bit | ||
! | ! Description | ||
|- | |- | ||
| 23-0 | | 23-0 | ||
| Line 113: | Line 113: | ||
== NDMA_BLOCK_CNT == | == NDMA_BLOCK_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! | ! Bit | ||
! | ! Description | ||
|- | |- | ||
| 15-0 | | 15-0 | ||
| Line 125: | Line 125: | ||
== NDMA_FILL_DATA == | == NDMA_FILL_DATA == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! | ! Bit | ||
! | ! Description | ||
|- | |- | ||
| 31-0 | | 31-0 | ||
| Line 136: | Line 136: | ||
! Bit | ! Bit | ||
! Description | ! Description | ||
|- | |||
| 4-0 | |||
| Device to device startup mode | |||
|- | |- | ||
| 11-10 | | 11-10 | ||
| Line 168: | Line 171: | ||
|} | |} | ||
== Startup modes ( | == Startup modes (4-0) == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Value | ! Value | ||
| Line 174: | Line 177: | ||
|- | |- | ||
| 0 | | 0 | ||
| TIMER0 | | TIMER0 | ||
|- | |- | ||
| 1 | | 1 | ||
| TIMER1 | | TIMER1 | ||
|- | |- | ||
| 2 | | 2 | ||
| TIMER2 | | TIMER2 | ||
|- | |- | ||
| 3 | | 3 | ||
| TIMER3 | | TIMER3 | ||
|- | |- | ||
| 4 | | 4 | ||
| Line 192: | Line 195: | ||
|- | |- | ||
| 6 | | 6 | ||
| | | SDIO1 | ||
|- | |- | ||
| 7 | | 7 | ||
| | | SDIO3 | ||
|- | |- | ||
| 8 | | 8 | ||
| AES | | AES in ([[AES_Registers#AES_WRFIFO.2FAES_RDFIFO|WRFIFO]]) | ||
|- | |- | ||
| 9 | | 9 | ||
| AES | | AES out ([[AES_Registers#AES_WRFIFO.2FAES_RDFIFO|RDFIFO]]) | ||
|- | |- | ||
| 10 | | 10 | ||
| SHA | | SHA in ([[SHA_Registers#SHA_FIFO|INFIFO]]) | ||
|- | |- | ||
| 11 | | 11 | ||
| | | SHA out ([[SHA_Registers#SHA_FIFO|INFIFO]], source data readback mode) | ||
|- | |- | ||
| 12 | | 12 | ||
| | | NTRCARD | ||
|- | |- | ||
| 13 | | 13 | ||
| Line 219: | Line 222: | ||
|- | |- | ||
| 15 | | 15 | ||
| AES | | Device to device (subclassed by bits 4-0) | ||
|} | |||
== Device to device startup modes (4-0) == | |||
{| class="wikitable" border="1" | |||
! Value | |||
! Description | |||
|- | |||
| 0 | |||
| CTRCARD0 -> AES | |||
|- | |||
| 1 | |||
| CTRCARD1 -> AES | |||
|- | |||
| 2 | |||
| AES -> CTRCARD0 | |||
|- | |||
| 3 | |||
| AES -> CTRCARD1 | |||
|- | |||
| 4 | |||
| CTRCARD0 -> SHA | |||
|- | |||
| 5 | |||
| CTRCARD1 -> SHA | |||
|- | |||
| 6 | |||
| SHA -> CTRCARD0 | |||
|- | |||
| 7 | |||
| SHA -> CTRCARD1 | |||
|- | |||
| 8 | |||
| SDIO1 -> AES | |||
|- | |||
| 9 | |||
| SDIO3 -> AES | |||
|- | |||
| 10 | |||
| AES -> SDIO1 | |||
|- | |||
| 11 | |||
| AES -> SDIO3 | |||
|- | |||
| 12 | |||
| SDIO1 -> SHA | |||
|- | |||
| 13 | |||
| SDIO3 -> SHA | |||
|- | |||
| 14 | |||
| SHA -> SDIO1 | |||
|- | |||
| 15 | |||
| SHA -> SDIO3 | |||
|- | |||
| 16 | |||
| AES -> SHA | |||
|- | |||
| 17 | |||
| SHA -> AES | |||
|} | |} | ||