RSA Registers: Difference between revisions
Clarifications and edge cases |
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| [[#RSA_EXPFIFO|RSA_EXPFIFO]] | | [[#RSA_EXPFIFO|RSA_EXPFIFO]] | ||
| 0x1000B200 | | 0x1000B200 | ||
| | | 0x100 (can handle u32 writes to any aligned position in the FIFO) | ||
| | | | ||
|- | |- | ||
| Line 78: | Line 78: | ||
|- | |- | ||
| 1 | | 1 | ||
| | | Interrupt enable (1=enable, 0=disable) | ||
|- | |- | ||
| 4-7 | | 4-7 | ||
| Line 124: | Line 124: | ||
| Key write-protect, this bit is RW. (0 = no protection, 1 = protected) | | Key write-protect, this bit is RW. (0 = no protection, 1 = protected) | ||
|- | |- | ||
| 30- | | 2 | ||
| Key read-protect, this bit is RW. (0 = no protection, 1 = protected) | |||
|- | |||
| 30-3 | |||
| ? | | ? | ||
|- | |- | ||
| 31 | | 31 | ||
| | | Key slot protect. Makes all other bits in this reg read-only until reset | ||
|} | |} | ||