MTX Registers: Difference between revisions
m Added missing interrupt register |
Update MTX bits and interrupts |
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| 0x1EC1x00C | | 0x1EC1x00C | ||
| | | [[#MTX_IE|MTX_IE]] | ||
| 4 | | 4 | ||
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==Matrix unit== | ==Matrix unit== | ||
There are two matrix units, one at +0x200, and the other one at +0x300 | There are two matrix units, one at +0x200 for vertical (Y) scaling, and the other one at +0x300 for horizontal (X) scaling. | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
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| 4 | | 4 | ||
| Kernel width - 1 is written here, 1 <= width <= 8 | | Kernel width - 1 is written here, 1 <= width <= 8 | ||
This decides how many pixels are written each batch. | |||
|- | |- | ||
| 0x1EC1xn04 | | 0x1EC1xn04 | ||
| KRN_PATTERN_BITS | | KRN_PATTERN_BITS | ||
| 4 | | 4 | ||
| If the corresponding bit is set then a new pixel is read | | If the corresponding bit for the current batch iteration index is set then a new pixel is read. | ||
The amount of set bits determine how many pixels are read each batch. Any bit indexes past KRN_WIDTH are ignored. | |||
This value is | This value is 8 bits, but it has to be written with a 32bit write. | ||
|- | |- | ||
| 0x1EC1xn40 | | 0x1EC1xn40 | ||
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|- | |- | ||
|} | |} | ||
=Descriptions= | =Descriptions= | ||
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|- | |- | ||
| 1 | | 1 | ||
| | | Enable vertical matrix | ||
|- | |- | ||
| 2 | | 2 | ||
| ??? | | Enable horizontal matrix | ||
|- | |||
| 4 | |||
| ??? | |||
|- | |||
| 5 | |||
| ??? | |||
|- | |- | ||
| 8-9 | | 8-9 | ||
| | | Input pixel mode? 0 = 4byte color, 1 = 3byte color, 2 = 2byte color, 3 = 2byte color | ||
|- | |- | ||
| 10-11 | | 10-11 | ||
| | | Output framebuffer rotation: 0 = normal, 1 = 90° CW (right), 2 = 180° CW (upside down, not mirrored), 3 = 270° CW (left) | ||
|- | |- | ||
| 12 | | 12 | ||
| | | Output tiling for use with the GPU. When set, the output width and height must be a multiple of 8. | ||
|- | |- | ||
| 15 | | 15 | ||
| | | Start bit (setting this will eventually raise MTX interrupt 0) | ||
|- | |- | ||
| 16 | | 16 | ||
| ? | | Data still available flag (?) | ||
|- | |- | ||
|} | |} | ||
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|- | |- | ||
| 0-8 | | 0-8 | ||
| Output framebuffer width - 1 is written here | | Output framebuffer width - 1 is written here, 1 <= width <= 512 | ||
|- | |- | ||
| 16-25 | | 16-25 | ||
| Output framebuffer height - 1 is written here | | Output framebuffer height - 1 is written here, 1 <= height <= 512 | ||
|- | |- | ||
|} | |} | ||
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Reading this register will return pending interrupts. | Reading this register will return pending interrupts. | ||
Writing this register will acknowledge the | Writing this register will acknowledge pending interrupts where the bits are set. | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
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|- | |- | ||
| 0 | | 0 | ||
| | | FIFO ready (signal to start DMA) | ||
|- | |- | ||
| 1 | | 1 | ||
| | | FIFO overrun(?) (occurs if DMA is too slow) | ||
|- | |- | ||
| 2 | | 2 | ||
| | | FIFO underrun(?) (occurs on VBlank) | ||
|- | |- | ||
|} | |} | ||
==MTX_IE== | |||
Interrupt Enable for the above interrupts. | |||