MTX Registers: Difference between revisions
Document more matrix unit bits |
Update MTX bits and interrupts |
||
| Line 25: | Line 25: | ||
|- | |- | ||
| 0x1EC1x00C | | 0x1EC1x00C | ||
| | | [[#MTX_IE|MTX_IE]] | ||
| 4 | | 4 | ||
|- | |- | ||
| Line 76: | Line 76: | ||
|- | |- | ||
| 0 | | 0 | ||
| Enable bit | | Enable bit | ||
|- | |- | ||
| 1 | | 1 | ||
| Line 100: | Line 100: | ||
|- | |- | ||
| 15 | | 15 | ||
| | | Start bit (setting this will eventually raise MTX interrupt 0) | ||
|- | |- | ||
| 16 | | 16 | ||
| Line 124: | Line 124: | ||
Reading this register will return pending interrupts. | Reading this register will return pending interrupts. | ||
Writing this register will acknowledge the | Writing this register will acknowledge pending interrupts where the bits are set. | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
| Line 131: | Line 131: | ||
|- | |- | ||
| 0 | | 0 | ||
| | | FIFO ready (signal to start DMA) | ||
|- | |- | ||
| 1 | | 1 | ||
| | | FIFO overrun(?) (occurs if DMA is too slow) | ||
|- | |- | ||
| 2 | | 2 | ||
| | | FIFO underrun(?) (occurs on VBlank) | ||
|- | |- | ||
|} | |} | ||
==MTX_IE== | |||
Interrupt Enable for the above interrupts. | |||