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| | 0x00010000 | | | 0x00010000 |
| | GetWakeStatus. This loads [[PDN Registers#PDN_WAKE_ENABLE|PDN_WAKE_ENABLE]] and [[PDN Registers#PDN_WAKE_REASON|PDN_WAKE_REASON]], then writes them to cmdreplyword[2] and cmdreplyword[3]. | | | [[PDNS:GetWakeStatus|GetWakeStatus]] |
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| | 0x00020080 | | | 0x00020080 |
| | ConfigureWakeEvents. [[PDN Registers#PDN_WAKE_REASON|PDN_WAKE_REASON]] = cmdword[2] & cmdword[1]. This then writes cmdword[1] to [[PDN Registers#PDN_WAKE_ENABLE|PDN_WAKE_ENABLE]]. [[PDN Registers#PDN_WAKE_REASON|PDN_WAKE_REASON]] = cmdword[2] & ~cmdword[1]. | | | [[PDNS:ConfigureWakeEvents|ConfigureWakeEvents]] |
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| | 0x00030040 | | | 0x00030040 |
| | Acknowledge. Writes cmdword[1] to [[PDN Registers#PDN_WAKE_REASON|PDN_WAKE_REASON]]. | | | [[PDNS:Acknowledge|Acknowledge]] |
| |} | | |} |
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| | 0x000100C0 | | | 0x000100C0 |
| | (bool enable, bool reset, bool deassertResetAfterReset) Enables and/or resets the DSP and/or holds it in reset | | | [[PDND:Control|Control]] |
| |} | | |} |
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| | 0x00010040 | | | 0x00010040 |
| | This sets bit0 in [[PDN Registers#PDN_I2S_CNT|PDN_I2S_CNT]] to u8 cmd+4. | | | [[PDNI:Control1|Control1]] |
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| | 0x00020040 | | | 0x00020040 |
| | This sets bit1 in [[PDN Registers#PDN_I2S_CNT|PDN_I2S_CNT]] to u8 cmd+4. | | | [[PDNI:Control2|Control2]] |
| |} | | |} |
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| | 0x000100C0 | | | 0x000100C0 |
| | (bool enableClock, bool resetEngines, bool resetRegisters) Enables and/or resets the GPU, see [[PDN Registers#PDN_GPU_CNT|PDN_GPU_CNT]] | | | [[PDNG:Control|Control]] |
| |} | | |} |
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| | 0x00010040 | | | 0x00010040 |
| | This sets bit0 in [[PDN Registers#PDN_CAMERA_CNT|PDN_CAMERA_CNT]] to u8 cmd+4. | | | [[PDNC:Control|Control]] |
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| | 0x000200000 | | | 0x000200000 |
| | This writes [[PDN Registers#PDN_CAMERA_CNT|PDN_CAMERA_CNT]] & 1 to u8 cmdreply+8. | | | [[PDNC:IsEnabled|IsEnabled]] |
| |} | | |} |