CONFIG11 Registers: Difference between revisions
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* CTR: O3DS | * CTR: O3DS | ||
* LGR1: N3DS prototype, 2 | * LGR1: N3DS prototype, 4 cores (orginally 2), up to 535MHz, no L2C (see below) | ||
* LGR2: retail N3DS, 4 cores, has L2C | * LGR2: retail N3DS, 4 cores, up to 804MHz, has L2C | ||
Kernel code suggests that devices that support LGR1 but not LGR2 only had 2 cores. All cores (the number of which can be read from MPCORE SCU registers) are usable in LGR1 mode. | |||
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