IO Registers: Difference between revisions

! Old3DS

! Category

! Physaddr

! Used by

| [[CONFIG9 Registers]]

| Boot9, Process9

| [[IRQ Registers]]

| Boot9, Process9, Kernel9

| ARM9 Interrupt Masking

| [[NDMA Registers]]

| Boot9, Process9

| AHB DMA Engine

| [[TIMER Registers]]

| Boot9, Process9

| [[CTRCARD Registers]]

| Process9

| [[EMMC Registers]]

| Boot9, Process9, NewKernel9Loader

| SD(IO) controller 1 and 3. 3 is normally mapped to ARM11.

| [[PXI Registers]]

| Boot9, Process9

| [[AES Registers]]

| Boot9, Process9, NewKernel9Loader

| [[SHA Registers]]

| Boot9, Process9, NewKernel9Loader

| [[RSA Registers]]

| Boot9, Process9

| [[Corelink DMA Engines|XDMA Registers]]

| Boot9, Kernel9

| [http://infocenter.arm.com/help/topic/com.arm.doc.subset.primecell.system/index.html CoreLink™ DMA-330 r0p0] (AXI busmaster, two channels, uses 32-bit bus width instead of 64).

| [[SPICARD Registers]]

| [[OTP Registers]]

| 0x10012000

| Boot9, Kernel9, NewKernel9Loader

| Top secret.

| style="background: green" | Yes

| TwlProcess9

| Used to setup the ARM7 core for AGB/TWL

| TMIO SD(IO) controller 3

| NWM references this controller but doesn't have access to it.

| [[HASH Registers]]

| [[Filesystem services]]

| These registers function the same as the [[SHA Registers]], with the exception of the FIFO being located at 0x10301000.

|-

| style="background: green" | Yes

| TwlBg

| [[Camera Services]]

| A11/A9

| 0x10122000

| [[NWM Services]]

| [[MVD Registers]]

| [[CONFIG11 Registers]]

| Process9, Boot11, Kernel11, TwlBg, [[DSP Services]], [[SPI Services]], [[NWM Services]] (until [[11.4.0-37#NWM-sysmodule|11.4.X]])

| System configuration.

| [[PDN Registers]]

| Process9, Boot11, Kernel11, TwlBg, [[Codec Services]], [[NWM Services]], [[SPI Services]], [[PDN Services]]

| Power management

| [[SPI Registers]]

| TwlBg, [[SPI Services]]

| [[SPI Registers]]

| TwlBg, dmnt Module

| Debugger related?

| [[I2C Registers]]

| Boot11, Kernel11, TwlBg, [[I2C Services]]

| 3DS I2C interface (MCU + Cameras + LCD)

| [[I2S Registers]]

| TwlBg, AgbBg, [[Codec Services]]

| Sound input/output lines

| style="background: green" | Yes

| A11/A9

| [[HID Registers]]

| Boot9, Boot11, Kernel11, TwlBg, [[HID Services]], dlp Services

| See [[PAD]].

| [[GPIO Registers]]

| Boot11, TwlBg, [[GPIO Services]], [[DSP Services]](v0)

| [[I2C Registers]]

| TwlBg, [[I2C Services]]

|-style="border-top: double"

| style="background: green" | Yes

| A11/A9

| [[SPI Registers]]

| Boot9, TwlBg, [[SPI Services]]

| [[I2C Registers]]

| Boot11, TwlBg, [[I2C Services]]

| TWL I2C interface (MCU + Cameras)

| [[MIC Registers]]

| [[MIC Services]]

| [[PXI Registers]]

| Boot11, Kernel11, TwlBg, [[PXI Services]]

| [[NTRCARD Registers]]

| Boot9, Process9

| [[MP Registers]]

| [[MP Services]]

| [[MP Registers]]

| [[MP Services]]

| NTR WIFI RAM

|-

| style="background: green" | Yes

|  [[MP Registers]]

| 0x10177000

|?

| NTR WIFI Registers (mirror)

| [[MP Registers]]

| [[Corelink DMA Engines|CDMA]]

| Boot11, Kernel11

| [http://infocenter.arm.com/help/topic/com.arm.doc.subset.primecell.system/index.html CoreLink™ DMA-330 r0p0] (eight channels). Only used by bootrom on New3DS.

| style="background: green" | Yes

| [[DSP Registers]]

| [[DSP Services]]

| see the "DSi XpertTeak" section in [http://problemkaputt.de/gba.htm no$gba] help.

| style="background: red" | No

| New 3DS only?

| TwlBg, [[GSP Services]]

| A11

| AHB (or AXI?) FIFOs region

| 0x10300000-0x10340000

|

| Pages present in this region correspond to the same respective devices in the 0x10100000-0x10140000 region but don't hold the same registers. They hold the FIFOs instead: the HASH FIFO register is located at 0x10301000. The LgyFb scaler data FIFO are located at 0x10310000 (top) and 0x10311000 (bot), etc. Needed for DMA.

|-style="border-top: double"

| style="background: green" | Yes

| A11

| [[GPU/External_Registers|GPU Registers]]

| Boot11, Kernel11, [[GSP Services]]

||

IO registers starting at physical address 0x10200000 are not accessible from the ARM9 (which includes all LCD/GPU registers). It seems IO registers below physical address 0x10100000 are not accessible from the ARM11 bus.