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GPU/Shader Instruction Set: Difference between revisions

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Registers within the 0x20-0x40 ranges seem to be RW. They contain uniforms, such as matrix data.
Registers within the 0x20-0x40 ranges seem to be RW. They contain uniforms, such as matrix data.


It appears that SRC1 and SRC2 operands don't map to registers in the same way. SRC1 is mapped to RO input registers (attributes and uniforms), while SRC2 is mapped to RW register and some RO input registers (attributes). DST is mapped to WO output registers and RW registers. As such, a register written to by an instruction cannot be referenced by SRC1, but it can be referenced by SRC2.
SRC2 being only 5 bits long rather than 7 bits like its friend SRC1, it can only access v (input attribute) and r (temporary) registers.


Registers in the 0x88-0x97 range are uniform booleans.
Registers in the 0x88-0x97 range are uniform booleans.
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