GPU/Shader Instruction Set: Difference between revisions
m opdesc negation bits (thanks neobrain) |
added MAD format |
||
| Line 134: | Line 134: | ||
| 0x1A | | 0x1A | ||
| 0x6 | | 0x6 | ||
| Opcode | |||
|} | |||
Format 5 : (used for MAD) | |||
{| class="wikitable" border="1" | |||
|- | |||
! Offset | |||
! Size (bits) | |||
! Description | |||
|- | |||
| 0x0 | |||
| 0x5 | |||
| Operand descriptor ID (DESC) | |||
|- | |||
| 0x5 | |||
| 0x5 | |||
| Source 2 register (SRC2) | |||
|- | |||
| 0xA | |||
| 0x7 | |||
| Source 1 register (SRC1) | |||
|- | |||
| 0x11 | |||
| 0x7 | |||
| Source 3 register (SRC3) | |||
|- | |||
| 0x18 | |||
| 0x5 | |||
| Destination register (DST) | |||
|- | |||
| 0x1D | |||
| 0x3 | |||
| Opcode | | Opcode | ||
|} | |} | ||