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GPU/Shader Instruction Set: Difference between revisions

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Smea (talk | contribs)
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m MAD operand order
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These indices are analogous to ARB's address registers.
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|  0x13
|  0x13
|  0x2
|  0x2
|  Index (IDX)
|  Address register index (IDX)
|-
|-
|  0x15
|  0x15
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|  0x13
|  0x13
|  0x2
|  0x2
|  Index (IDX)
|  Address register index (IDX)
|-
|-
|  0x15
|  0x15
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|  0x12
|  0x12
|  1
|  1
|  SETIDX
|  ARL
|  Sets (idx1, idx2, _, _) to SRC1 (cast to integer).  
|  Address Register Load; sets (a0, a1, _, _) to SRC1 (cast to integer).
|-
|-
|  0x13
|  0x13
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== Relative addressing ==
== Relative addressing ==


There are 3 global index registers : idx1, idx2 and idx3 = lcnt (loop counter). For format 1 instructions, when IDX != 0, the value of the corresponding index is added to SRC1's value.
There are 3 global address registers : a0, a1 and a2 = lcnt (loop counter). For format 1 instructions, when IDX != 0, the value of the corresponding address register is added to SRC1's value.


For example, if IDX = 2, idx2 = 3 and SRC1 = c8, then instead SRC1+idx2 = c11 will be used for the instruction.
For example, if IDX = 2, a1 = 3 and SRC1 = c8, then instead SRC1+a1 = c11 will be used for the instruction.


idx1 and idx2 can be set manually through the SETIDX instruction. lcnt is set automatically by the LOOP instruction. Note that lcnt is still accessible and valid after exiting a LOOP block.
a0 and a1 can be set manually through the ARL instruction. lcnt is set automatically by the LOOP instruction. Note that lcnt is still accessible and valid after exiting a LOOP block.


== Registers ==
== Registers ==
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