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GPU/Shader Instruction Set: Difference between revisions

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Neobrain (talk | contribs)
549 edits
These indices are analogous to ARB's address registers.
Smea (talk | contribs)
373 edits
m →Registers: clarification
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SRC1 mapping :
SRC mapping :


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SRC2 mapping :
Not that 5bit SRC registers (SRC2 in format 1 for example) can't access c0-c95 because they don't have enough bits.
 
{| class="wikitable" border="1"
|-
!  SRC2 raw value
!  Register name
!  Description
|-
|  0x0-0x7
|  v0-v7
|  Input attribute registers.
|-
|  0x10-0x1F
|  r0-r15
|  Temporary registers.
|}
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