GPU/Shader Instruction Set: Difference between revisions

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 Please note that this page is being written as the instruction set is reverse engineered; as such it may very well contain mistakes.
-Nomenclature :
+== Nomenclature ==
-- opcode names with I appended to them are the same as their non-I version, except they use the inverted instruction format, giving 7 bits to SRC2 (and access to uniforms) and 5 bits to SRC1
+* opcode names with I appended to them are the same as their non-I version, except they use the inverted instruction format, giving 7 bits to SRC2 (and access to uniforms) and 5 bits to SRC1
-- opcode names with U appended to them are the same as their non-U version, except they are executed conditionally based on the value of a uniform boolean.
+* opcode names with U appended to them are the same as their non-U version, except they are executed conditionally based on the value of a uniform boolean.
-- opcode names with C appended to them are the same as their non-C version, except they are executed conditionally based on a logical expression specified in the instruction.
+* opcode names with C appended to them are the same as their non-C version, except they are executed conditionally based on a logical expression specified in the instruction.
 == Instruction formats ==