SPI Registers: Difference between revisions
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Line 17: | Line 17: | ||
| 0x10142002 | | 0x10142002 | ||
| 1 | | 1 | ||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]0 | |||
| 0x10142800 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| SPI_NEW_???0 | |||
| 0x10142804 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]0 | |||
| 0x10142808 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]0 | |||
| 0x1014280C | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]0 | |||
| 0x101428010 | |||
| 4 | |||
| | | | ||
|- | |- | ||
Line 29: | Line 59: | ||
| 0x10143002 | | 0x10143002 | ||
| 1 | | 1 | ||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]1 | |||
| 0x10143800 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| SPI_NEW_???1 | |||
| 0x10143804 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]1 | |||
| 0x10143808 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]1 | |||
| 0x1014380C | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]1 | |||
| 0x101438010 | |||
| 4 | |||
| | | | ||
|- | |- | ||
Line 41: | Line 101: | ||
| 0x10160002 | | 0x10160002 | ||
| 1 | | 1 | ||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]2 | |||
| 0x10160800 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| SPI_NEW_???2 | |||
| 0x10160804 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]2 | |||
| 0x10160808 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]2 | |||
| 0x1016080C | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]2 | |||
| 0x101608010 | |||
| 4 | |||
| | | | ||
|} | |} | ||
== SPI_CNT == | == SPI_CNT == | ||
This is the old NDS/DSi SPI interface. | |||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Old3DS | ! Old3DS | ||
Line 76: | Line 168: | ||
| SPI Bus Enable (0=Disable, 1=Enable) | | SPI Bus Enable (0=Disable, 1=Enable) | ||
|} | |} | ||
== SPI_NEW_CNT == | |||
This is an alternative faster interface introduced with the 3DS. | |||
{| class="wikitable" border="1" | |||
! Old3DS | |||
! Name | |||
|- | |||
| 6-7 | |||
| Device Select | |||
|- | |||
| 13 | |||
| Transfer Direction? (0=Incoming, 1=Outgoing) | |||
|- | |||
| 15 | |||
| Busy/enable | |||
|} | |||
==SPI_NEW_BLKLEN== | |||
The number of bytes to be sent/read is written to this register. | |||
==SPI_NEW_FIFO== | |||
32-bit FIFO for reading/writing the SPI payload. | |||
==SPI_NEW_STATUS== | |||
Bit0: FIFO busy. |
Revision as of 22:38, 21 March 2015
Registers
Old3DS | Name | Address | Width | Used by |
---|---|---|---|---|
Yes | SPI_CNT0 | 0x10142000 | 2 | |
Yes | SPI_DATA0 | 0x10142002 | 1 | |
Yes | SPI_NEW_CNT0 | 0x10142800 | 4 | |
Yes | SPI_NEW_???0 | 0x10142804 | 4 | |
Yes | SPI_NEW_BLKLEN0 | 0x10142808 | 4 | |
Yes | SPI_NEW_FIFO0 | 0x1014280C | 4 | |
Yes | SPI_NEW_STATUS0 | 0x101428010 | 4 | |
Yes | SPI_CNT1 | 0x10143000 | 2 | |
Yes | SPI_DATA1 | 0x10143002 | 1 | |
Yes | SPI_NEW_CNT1 | 0x10143800 | 4 | |
Yes | SPI_NEW_???1 | 0x10143804 | 4 | |
Yes | SPI_NEW_BLKLEN1 | 0x10143808 | 4 | |
Yes | SPI_NEW_FIFO1 | 0x1014380C | 4 | |
Yes | SPI_NEW_STATUS1 | 0x101438010 | 4 | |
Yes | SPI_CNT2 | 0x10160000 | 2 | |
Yes | SPI_DATA2 | 0x10160002 | 1 | |
Yes | SPI_NEW_CNT2 | 0x10160800 | 4 | |
Yes | SPI_NEW_???2 | 0x10160804 | 4 | |
Yes | SPI_NEW_BLKLEN2 | 0x10160808 | 4 | |
Yes | SPI_NEW_FIFO2 | 0x1016080C | 4 | |
Yes | SPI_NEW_STATUS2 | 0x101608010 | 4 |
SPI_CNT
This is the old NDS/DSi SPI interface.
Old3DS | Name |
---|---|
0-1 | Baudrate (0=4MHz/Firmware, 1=2MHz/Touchscr, 2=1MHz/Powerman., 3=512KHz) |
2-6 | Not used (Zero) |
7 | Busy Flag (0=Ready, 1=Busy) (presumably Read-only) |
8-9 | Device Select (0-3) |
10 | Transfer Size (0=8bit/Normal, 1=16bit/Bugged) |
11 | Chipselect Hold (0=Deselect after transfer, 1=Keep selected) |
12-13 | Not used (Zero) |
14 | Interrupt Request (0=Disable, 1=Enable) |
15 | SPI Bus Enable (0=Disable, 1=Enable) |
SPI_NEW_CNT
This is an alternative faster interface introduced with the 3DS.
Old3DS | Name |
---|---|
6-7 | Device Select |
13 | Transfer Direction? (0=Incoming, 1=Outgoing) |
15 | Busy/enable |
SPI_NEW_BLKLEN
The number of bytes to be sent/read is written to this register.
SPI_NEW_FIFO
32-bit FIFO for reading/writing the SPI payload.
SPI_NEW_STATUS
Bit0: FIFO busy.