ARM11 Interrupts: Difference between revisions
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= Private Interrupts = | |||
Each CPU core has 32 software interrupts that are private and belong to that core. These interrupts are numbers 0-0x1F for each core. The hardware interrupts are not core-specific and start at interrupt ID 0x20. | |||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! IRQ | ! IRQ | ||
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| kernel | | kernel | ||
| MPCore watchdog. | | MPCore watchdog. | ||
|} | |||
= Hardware Interrupts = | |||
There are 0x60 hardware interrupts starting at 0x20 and continuing up to 0x7F. These are not private and are accessible from any core. | |||
{| class="wikitable" border="1" | |||
! IRQ | |||
! Listener | |||
! Description | |||
|- | |- | ||
| 0x28 | | 0x28 | ||
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| ? | | ? | ||
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There are 2 tables in the ARM11 kernel: the first has 32 * 2(or 32 * 4) 8-byte entries. This table is for the private interrupts that belong to each core. The data for each interrupt can be found by doing table_base + (core_num * 0x100) + (intr_num * 8). The second table is for public hardware interrupts and the data for each interrupt can be retrieved by doing table_base + (intr_num * 8). | |||