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GPU/Internal Registers: Difference between revisions

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| Enabled (0 = disabled, 1 = enabled)
| Enabled (0 = disabled, 1 = enabled)
|}
|}
=== GPUREG_TEXUNIT3_PROCTEX0 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| U-direction clamp
|-
| 3-5
| V-direction clamp
|-
| 6-9
| RGB mapping function
|-
| 10-13
| Alpha mapping function
|-
| 14
| Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| U-direction shift
|-
| 18-19
| V-direction shift
|-
| 20-27
| float16 low 8 bits, Texture bias
|}
Clamp values:
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}
Mapping function values:
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U2
|-
| 2
| V
|-
| 3
| V2
|-
| 4
| U + V
|-
| 5
| U2 + V2
|-
| 6
| sqrt(U2 + V2)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}
Shift values:
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}
=== GPUREG_TEXUNIT3_PROCTEX1 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float16, U-direction noise phase
|-
| 16-31
| fixed16, U-direction noise amplitude
|}
=== GPUREG_TEXUNIT3_PROCTEX2 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float16, V-direction noise phase
|-
| 16-31
| fixed16, V-direction noise amplitude
|}
=== GPUREG_TEXUNIT3_PROCTEX3 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float16, U-direction noise frequency
|-
| 16-31
| float16, V-direction noise frequency
|}
=== GPUREG_TEXUNIT3_PROCTEX4 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| Minification filter
|-
| 3-10
| 0x60
|-
| 11-18
| Texture width
|-
| 19-26
| float16 high 8 bits, Texture bias
|}
Minification filter values:
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}
=== GPUREG_TEXUNIT3_PROCTEX5 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Texture offset
|-
| 8-31
| 0xE0C080
|}
=== GPUREG_PROCTEX_LUT ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| Index
|-
| 8-11
| Reference table
|}
Reference tables:
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}
==== Noise Table ====
128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned fixed12, Value
|-
| 12-23
| signed fixed12, Difference from next element
|}
==== RGB Mapping Function Table ====
128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned fixed12, Value
|-
| 12-23
| signed fixed12, Difference from next element
|}
==== Alpha Mapping Function Table ====
128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned fixed12, Value
|-
| 12-23
| signed fixed12, Difference from next element
|}
==== Color Table ====
256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| u8, Red
|-
| 8-15
| u8, Green
|-
| 16-23
| u8, Blue
|-
| 24-31
| u8, Alpha
|}
==== Color Difference Table ====
256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed fixed8, Red difference between current and next color table elements
|-
| 8-15
| signed fixed8, Green difference between current and next color table elements
|-
| 16-23
| signed fixed8, Blue difference between current and next color table elements
|-
| 24-31
| signed fixed8, Alpha difference between current and next color table elements
|}
=== GPUREG_PROCTEX_LUT_DATA''i'' ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, sequentially.


== Framebuffer registers ==
== Framebuffer registers ==
Retrieved from "https://www.3dbrew.org/wiki/GPU/Internal_Registers"