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Corelink DMA Engines: Difference between revisions

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     sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.
     sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.
     uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.
     uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.
     uint8_t flags; // @2 bit0: DST_CFG, bit1: SRC_CFG, bit2: SHALL_BLOCK, bit3: KEEP_ALIVE, bit6: DST_ALT_CFG, bit7: SRC_ALT_CFG
     uint8_t flags; // @2 bit0: DST_IS_PERIPHERAL, bit1: SRC_IS_PERIPHERAL, bit2: SHALL_BLOCK, bit3: KEEP_ALIVE, bit6: DST_IS_RAM, bit7: SRC_IS_RAM
     uint8_t padding;
     uint8_t padding;
     DmaSubConfig dst_cfg;
     DmaSubConfig dst_cfg;
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  struct DmaSubConfig {
  struct DmaSubConfig {
     sint8_t peripheral_id; // @0 If not *_ALT_CFG set, this must be < 0x1E.
     sint8_t peripheral_id; // @0 If not *_IS_RAM set, this must be < 0x1E.
     uint8_t burst_size_raw; // (1 << raw size) bytes, bit4 is ignored? // @1 Accepted values: 4=fixed_addr??, 8=increment_addr??, 12=lgy_fb_copy?, 15=userspace_copy? (??)
     uint8_t allowed_burst_sizes; // @1 Accepted values: 4, 8, 4|8 = 12, 1|2|4|8 = 15  
     sint16_t max_burst_size_bits; // @2 Must be 0 or multiple of 4?
     sint16_t max_burst_total; // @2 Burst length * burst size
     sint16_t transfer_size?; // @4 Must not be 0 if peripheral_id == 0xFF.
     sint16_t transfer_size?; // @4 Must not be 0 if peripheral_id == 0xFF.
     sint16_t unk4; // @6
     sint16_t unk4; // @6
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  }
  }


If SRC_CFG/DST_CFG is set in the flags field, the configuration for src/dst is loaded from src_cfg/dst_cfg respectively. If the *_ALT_CFG flag is set same thing goes, except byte0 of each cfg is forced to 0xFF. ALT_CFG has priority over CFG.
If SRC_IS_PERIPHERAL/SRC_IS_PERIPHERAL is set in the flags field, the configuration for src/dst is loaded from src_cfg/dst_cfg respectively and the transfer will be done from/to a fixed address. If the *_IS_RAM flag is set same thing goes, except byte0 of each cfg is forced to 0xFF (RAM) and the transfer will be done from/to an incrementing address. *_IS_RAM has priority over _IS_PERIPHERAL.


If CFG or ALT_CFG is not set, default configuration is loaded:
If neither *_IS_PERIPHERAL or *_IS_RAM is set, default configuration is loaded:


  .peripheral_id = 0xFF,
  .peripheral_id = 0xFF,
  .unk2 = 0xF,
  .allowed_burst_sizes = 1 | 2 | 4 | 8,
  .unk3 = 0x80,
  .max_burst_total = 0x80,
  .transfer_size = 0,
  .transfer_size? = 0,
  .unk4 = 0x80,
  .unk4 = 0x80,
  .unk5 = 0,
  .transfer_stride? = 0,
 
Checks suggest that unk2 of DmaSubConfig equalling 4 means NO_INCREMENT (don't increment after read/write).


If SHALL_BLOCK is set, the thread will sleep until the DMA engine is ready. If not set, the SVC will return 0xD04007F0 if the DMA channel is busy.
If SHALL_BLOCK is set, the thread will sleep until the DMA engine is ready. If not set, the SVC will return 0xD04007F0 if the DMA channel is busy.
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!  Description
!  Description
|-
|-
| 0 (?)
| 0
| Process9
| Process9
| CTRCARD
| CTRCARD
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