GPU/Internal Registers: Difference between revisions

Wwylele (talk | contribs)
GPUREG_TEXUNIT3_PROCTEX5: Document more proctex mipmap configuration based on hardware test
Wwylele (talk | contribs)
Line 5,050: Line 5,050:
| 24-31
| 24-31
| unsigned, mipmap level 3 offset (usually 0xE0)
| unsigned, mipmap level 3 offset (usually 0xE0)
|-
|
| Note: mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE
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This register is used to set the procedural texture unit's offset.
This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .


=== GPUREG_PROCTEX_LUT ===
=== GPUREG_PROCTEX_LUT ===