GPU/External Registers: Difference between revisions
Start cleaning up rotated screen clutter from PDC reg descriptions and add some mroe info |
m Fix a missing brace in calculation and make register more clear |
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| Line 156: | Line 156: | ||
| The total width of a timing scanline. In other words, this is the horizontal refresh clock divider value. | | The total width of a timing scanline. In other words, this is the horizontal refresh clock divider value. | ||
HClock = PClock / ( | HClock = PClock / (HTotal + 1) | ||
|- | |- | ||
| 0x04 | | 0x04 | ||
| Line 218: | Line 218: | ||
| Total height of the timing window. Can be interpreted as the vertical clock divider. | | Total height of the timing window. Can be interpreted as the vertical clock divider. | ||
VClock = | VClock = PClock / (HTotal + 1) / (VTotal + 1) | ||
Setting this to 494 lowers framerate to about 50.040660858 Hz (268111856 / 24 / (250 + 1) / (494 + 1)). | Setting this to 494 lowers framerate to about 50.040660858 Hz ((268111856 / 24) / (250 + 1) / (494 + 1)). | ||
|- | |- | ||
| 0x28 | | 0x28 | ||