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GPU/External Registers: Difference between revisions

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MarcusD (talk | contribs)
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Update horizontal timing parameters (continuation)
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Line 32: Line 32:
| 4
| 4
| VRAM bank control
| VRAM bank control
| Bits 8-11 = bank[i] disabled; other bits are unused
| Bits 8-11 = bank[i] disabled; other bits are unused.
|-
|-
| 0x1EF00034
| 0x1EF00034
Line 38: Line 38:
| 4
| 4
| GPU Busy
| GPU Busy
| Bit31 = cmd-list busy, bit27 = PSC0 busy, bit26 = PSC1 busy.
| Bit26 = PSC0, bit27 = PSC1, Bit30 = PPF, Bit31 = P3D
|-
|-
| 0x1EF00050
| 0x1EF00050
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