GPU/Shader Instruction Set: Difference between revisions
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A compiled shader binary is comprised of two parts : the main instruction sequence and the operand descriptor table. These are both sent to the GPU around the same time but using separate [[GPU Commands]]. Instructions (such as format 1 instruction) may reference operand descriptors. When such is the case, the operand descriptor ID is the offset, in words, of the descriptor within the table. | A compiled shader binary is comprised of two parts : the main instruction sequence and the operand descriptor table. These are both sent to the GPU around the same time but using separate [[GPU Commands]]. Instructions (such as format 1 instruction) may reference operand descriptors. When such is the case, the operand descriptor ID is the offset, in words, of the descriptor within the table. | ||
Both instructions and descriptors are coded in little endian. | Both instructions and descriptors are coded in little endian. | ||
[https://github.com/smealum/aemstro] | A basic implementation of the following specification can be found at [https://github.com/smealum/aemstro] | ||
== Instruction formats == | == Instruction formats == | ||