GPU/Shader Instruction Set: Difference between revisions

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For example, if IDX = 2, idx2 = 3 and SRC1 = c8, then instead SRC1+idx2 = c11 will be used for the instruction.

idx1 and idx2 can be set manually through the ~~SETINDEX~~ instruction. lcnt is set automatically by the LOOP instruction. Note that lcnt is still accessible and valid after exiting a LOOP block.

idx1 and idx2 can be set manually through the SETIDX instruction. lcnt is set automatically by the LOOP instruction. Note that lcnt is still accessible and valid after exiting a LOOP block.

== Registers ==

~~It is not yet fully understood how registers~~ are organized. It does however seem that registers are separated into various banks, some RO, some WO and some RW. Because of this separation, a given register ID may not refer to the same register value when it is used as SRC or as DST.

Registers are float[4] vectors.

Attribute (input, RO) registers are located within the 0x0-~~0x10~~ range. What data they are fed is specified by the CPU.

Attribute (input, RO) registers are located within the 0x0-0xF range. What data they are fed is specified by the CPU.

Output (WO) registers are also located within the 0x0-~~0x10~~ range. What data they are contain is specified by the CPU.

~~Registers~~ within the ~~0x20~~-~~0x40 ranges seem to be RW~~. They contain ~~uniforms, such as matrix~~ data.

Output (WO) registers are also located within the 0x0-0xF range. What type of data they are contain is specified by the CPU.

Temporary (RW) register are located within the 0x10-0x1F range. They can contain any type of data.

Uniform (RO) registers are located within the 0x20-0x7F range. Their content is set by the CPU.

SRC2 being only 5 bits long rather than 7 bits like its friend SRC1, it can only access v (input attribute) and r (temporary) registers.

@@ Line 306: / Line 306: @@
 For example, if IDX = 2, idx2 = 3 and SRC1 = c8, then instead SRC1+idx2 = c11 will be used for the instruction.
-idx1 and idx2 can be set manually through the SETINDEX instruction. lcnt is set automatically by the LOOP instruction. Note that lcnt is still accessible and valid after exiting a LOOP block.
+idx1 and idx2 can be set manually through the SETIDX instruction. lcnt is set automatically by the LOOP instruction. Note that lcnt is still accessible and valid after exiting a LOOP block.
 == Registers ==
-It is not yet fully understood how registers are organized. It does however seem that registers are separated into various banks, some RO, some WO and some RW. Because of this separation, a given register ID may not refer to the same register value when it is used as SRC or as DST.
+Registers are float[4] vectors.
-Attribute (input, RO) registers are located within the 0x0-0x10 range. What data they are fed is specified by the CPU.
+Attribute (input, RO) registers are located within the 0x0-0xF range. What data they are fed is specified by the CPU.
-Output (WO) registers are also located within the 0x0-0x10 range. What data they are contain is specified by the CPU.
-Registers within the 0x20-0x40 ranges seem to be RW. They contain uniforms, such as matrix data.
+Output (WO) registers are also located within the 0x0-0xF range. What type of data they are contain is specified by the CPU.
+Temporary (RW) register are located within the 0x10-0x1F range. They can contain any type of data.
+Uniform (RO) registers are located within the 0x20-0x7F range. Their content is set by the CPU.
 SRC2 being only 5 bits long rather than 7 bits like its friend SRC1, it can only access v (input attribute) and r (temporary) registers.